[PATCH] [TSan][MIPS] Adding support for MIPS64
Sagar Thakur
Sagar.Thakur at imgtec.com
Wed Dec 24 05:57:58 PST 2014
> What is the main reason of unexpected failures in test?
Failing Tests (15):
ThreadSanitizer :: global_race.cc
ThreadSanitizer :: global_race2.cc
ThreadSanitizer :: global_race3.cc
ThreadSanitizer :: longjmp.cc
ThreadSanitizer :: longjmp2.cc
ThreadSanitizer :: longjmp3.cc
ThreadSanitizer :: longjmp4.cc
ThreadSanitizer :: map32bit.cc
ThreadSanitizer :: mmap_large.cc
ThreadSanitizer :: race_on_mutex.c
ThreadSanitizer :: signal_longjmp.cc
ThreadSanitizer :: signal_errno.cc
ThreadSanitizer :: stack_sync_reuse.cc
ThreadSanitizer :: tls_race.cc
ThreadSanitizer :: tls_race2.cc
global_race.cc, global_race2.cc, global_race3.cc : File Check expects a 47-bit address in place of ADDR, ADDR2, ADDR3 respectively. Where as MIPS64 uses 40-bit addresses.
longjmp.cc, longjmp2.cc, longjmp3.cc, longjmp4.cc, signal_longjmp.cc : We have not implemented longjmp/setjmp assemble for MIPS.
map32bit.cc : MAP_32BIT flag for mmap is supported only for x86_64.
mmap_large.cc : Mmap start address is given according to 47-bit address space. Where as MIPS64 uses 40-bit addresses.
race_on_mutex.c : Stack trace is incorrect because of interception of memset call from nptl/pthread_mutex_init.c:91 in glibc.
signal_errno.cc : Stack trace is incorrect because pc is incremented by 1 at tsan_interceptors.cc:1908 in CallUserSignalHandler (). Here, we need to use StackTrace::GetNextInstructionPC () in place of `pc +1`.
stack_sync_reuse.cc : There is address mismatch between addr and &s in the test case.
tls_race.cc : Test case passes on application of http://reviews.llvm.org/D5616 patch because this patch provides the definition of ThreadDescriptorSize (), GetTls () and ThreadSelf () for MIPS.
tls_race2.cc : ReportStackLocation is Stack instead of TLS. This is because there is an overlap between TLS and Stack address range.
REPOSITORY
rL LLVM
http://reviews.llvm.org/D6291
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