[llvm] r224774 - [Hexagon] Adding signed halfword loads.
Colin LeMahieu
colinl at codeaurora.org
Tue Dec 23 09:25:58 PST 2014
Author: colinl
Date: Tue Dec 23 11:25:57 2014
New Revision: 224774
URL: http://llvm.org/viewvc/llvm-project?rev=224774&view=rev
Log:
[Hexagon] Adding signed halfword loads.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=224774&r1=224773&r2=224774&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Tue Dec 23 11:25:57 2014
@@ -406,7 +406,7 @@ SDNode *HexagonDAGToDAGISel::SelectBaseO
// Figure out base + offset opcode
if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed;
else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed;
- else if (LoadedVT == MVT::i16) Opcode = Hexagon::LDrih_indexed;
+ else if (LoadedVT == MVT::i16) Opcode = Hexagon::L2_loadrh_io;
else if (LoadedVT == MVT::i8) Opcode = Hexagon::L2_loadrb_io;
else llvm_unreachable("unknown memory type");
@@ -607,7 +607,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndex
if (TII->isValidAutoIncImm(LoadedVT, Val))
Opcode = zextval ? Hexagon::POST_LDriuh : Hexagon::POST_LDrih;
else
- Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::LDrih;
+ Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
} else if (LoadedVT == MVT::i8) {
if (TII->isValidAutoIncImm(LoadedVT, Val))
Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::POST_LDrib;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=224774&r1=224773&r2=224774&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Tue Dec 23 11:25:57 2014
@@ -80,7 +80,7 @@ unsigned HexagonInstrInfo::isLoadFromSta
default: break;
case Hexagon::LDriw:
case Hexagon::LDrid:
- case Hexagon::LDrih:
+ case Hexagon::L2_loadrh_io:
case Hexagon::L2_loadrb_io:
case Hexagon::L2_loadrub_io:
if (MI->getOperand(2).isFI() &&
@@ -678,9 +678,8 @@ bool HexagonInstrInfo::isPredicable(Mach
case Hexagon::LDriw_indexed:
return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
- case Hexagon::LDrih:
+ case Hexagon::L2_loadrh_io:
case Hexagon::L2_loadruh_io:
- case Hexagon::LDrih_indexed:
return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
case Hexagon::L2_loadrb_io:
@@ -1122,7 +1121,7 @@ isValidOffset(const int Opcode, const in
return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
(Offset <= Hexagon_MEMD_OFFSET_MAX);
- case Hexagon::LDrih:
+ case Hexagon::L2_loadrh_io:
case Hexagon::L2_loadruh_io:
case Hexagon::STrih:
return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
@@ -1357,10 +1356,8 @@ isConditionalLoad (const MachineInstr* M
case Hexagon::LDriw_cNotPt :
case Hexagon::LDriw_indexed_cPt :
case Hexagon::LDriw_indexed_cNotPt :
- case Hexagon::LDrih_cPt :
- case Hexagon::LDrih_cNotPt :
- case Hexagon::LDrih_indexed_cPt :
- case Hexagon::LDrih_indexed_cNotPt :
+ case Hexagon::L2_ploadrht_io:
+ case Hexagon::L2_ploadrhf_io:
case Hexagon::L2_ploadrbt_io:
case Hexagon::L2_ploadrbf_io:
case Hexagon::L2_ploadruht_io:
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=224774&r1=224773&r2=224774&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Tue Dec 23 11:25:57 2014
@@ -1547,7 +1547,8 @@ let accessSize = ByteAccess, isCodeGenOn
defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
}
-let accessSize = HalfWordAccess, opExtentAlign = 1 in {
+let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
+ defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>;
defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
}
@@ -1591,10 +1592,6 @@ multiclass LD_MEMri<string mnemonic, str
}
let addrMode = BaseImmOffset, isMEMri = "true" in {
- let accessSize = HalfWordAccess in {
- defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
- }
-
let accessSize = WordAccess in
defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
@@ -1609,10 +1606,10 @@ def : Pat < (i32 (zextloadi8 ADDRriS11_0
(L2_loadrub_io AddrFI:$addr, 0) >;
def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
- (LDrih ADDRriS11_1:$addr) >;
+ (L2_loadrh_io AddrFI:$addr, 0) >;
def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
- (L2_loadrub_io AddrFI:$addr, 0) >;
+ (L2_loadruh_io AddrFI:$addr, 0) >;
def : Pat < (i32 (load ADDRriS11_2:$addr)),
(LDriw ADDRriS11_2:$addr) >;
@@ -1662,10 +1659,6 @@ multiclass LD_Idxd2<string mnemonic, str
}
let addrMode = BaseImmOffset in {
- let accessSize = HalfWordAccess in {
- defm LDrih_indexed: LD_Idxd2 <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
- 12, 7>, AddrModeRel;
- }
let accessSize = WordAccess in
defm LDriw_indexed: LD_Idxd2 <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
13, 8>, AddrModeRel;
@@ -1683,7 +1676,7 @@ def : Pat < (i32 (zextloadi8 (add IntReg
(L2_loadrub_io IntRegs:$src1, s11_0ExtPred:$offset) >;
def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
- (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
+ (L2_loadrh_io IntRegs:$src1, s11_1ExtPred:$offset) >;
def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
(L2_loadruh_io IntRegs:$src1, s11_1ExtPred:$offset) >;
@@ -1766,11 +1759,11 @@ def : Pat < (i32 (extloadi8 (add IntRegs
(i32 (L2_loadrb_io IntRegs:$src1, s11_0ImmPred:$offset)) >;
def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
- (i32 (LDrih ADDRriS11_1:$addr))>;
+ (i32 (L2_loadrh_io AddrFI:$addr, 0))>;
let AddedComplexity = 20 in
def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
- (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
+ (i32 (L2_loadrh_io IntRegs:$src1, s11_1ImmPred:$offset)) >;
let AddedComplexity = 10 in
def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
@@ -4030,7 +4023,7 @@ def: Pat <(i64 (extloadi8 ADDRriS11_0:$
// Convert sign-extended load back to load and sign extend.
// i16 -> i64
def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
- (i64 (A2_sxtw (LDrih ADDRriS11_1:$src1)))>;
+ (i64 (A2_sxtw (L2_loadrh_io AddrFI:$src1, 0)))>;
// Convert sign-extended load back to load and sign extend.
// i32 -> i64
@@ -4183,13 +4176,13 @@ def: Pat <(i64 (extloadi32 (i32 (add In
// anyext i16 -> i64.
def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
- (i64 (A2_combinew (A2_tfrsi 0), (LDrih ADDRriS11_2:$src1)))>,
+ (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrh_io AddrFI:$src1, 0)))>,
Requires<[NoV4T]>;
let AddedComplexity = 20 in
def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
s11_1ExtPred:$offset))),
- (i64 (A2_combinew (A2_tfrsi 0), (LDrih_indexed IntRegs:$src1,
+ (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrh_io IntRegs:$src1,
s11_1ExtPred:$offset)))>,
Requires<[NoV4T]>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=224774&r1=224773&r2=224774&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Tue Dec 23 11:25:57 2014
@@ -448,13 +448,13 @@ def: Pat <(i64 (zextloadi16 (add (i32 I
// anyext i16->i64
def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
- (i64 (COMBINE_Ir_V4 0, (LDrih ADDRriS11_2:$src1)))>,
+ (i64 (COMBINE_Ir_V4 0, (L2_loadrh_io AddrFI:$src1, 0)))>,
Requires<[HasV4T]>;
let AddedComplexity = 20 in
def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
s11_1ExtPred:$offset))),
- (i64 (COMBINE_Ir_V4 0, (LDrih_indexed IntRegs:$src1,
+ (i64 (COMBINE_Ir_V4 0, (L2_loadrh_io IntRegs:$src1,
s11_1ExtPred:$offset)))>,
Requires<[HasV4T]>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp?rev=224774&r1=224773&r2=224774&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp Tue Dec 23 11:25:57 2014
@@ -161,7 +161,7 @@ void HexagonRegisterInfo::eliminateFrame
// r0 = memw(r0)
if ( (MI.getOpcode() == Hexagon::LDriw) ||
(MI.getOpcode() == Hexagon::LDrid) ||
- (MI.getOpcode() == Hexagon::LDrih) ||
+ (MI.getOpcode() == Hexagon::L2_loadrh_io) ||
(MI.getOpcode() == Hexagon::L2_loadruh_io) ||
(MI.getOpcode() == Hexagon::L2_loadrb_io) ||
(MI.getOpcode() == Hexagon::L2_loadrub_io) ||
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt?rev=224774&r1=224773&r2=224774&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt Tue Dec 23 11:25:57 2014
@@ -12,6 +12,8 @@
0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x47
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memb(r21 + #44)
+0xf1 0xc3 0x55 0x91
+# CHECK: r17 = memh(r21 + #62)
0xf1 0xc3 0x35 0x91
# CHECK: r17 = memub(r21 + #31)
0xf1 0xdb 0x35 0x41
@@ -24,3 +26,15 @@
0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x47
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memub(r21 + #31)
+0xb1 0xc2 0x75 0x91
+# CHECK: r17 = memuh(r21 + #42)
+0xb1 0xda 0x75 0x41
+# CHECK: if (p3) r17 = memuh(r21 + #42)
+0xb1 0xda 0x75 0x45
+# CHECK: if (!p3) r17 = memuh(r21 + #42)
+0x03 0x40 0x45 0x85 0xb1 0xda 0x75 0x43
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = memuh(r21 + #42)
+0x03 0x40 0x45 0x85 0xb1 0xda 0x75 0x47
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = memuh(r21 + #42)
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