[llvm] r224758 - [PowerPC] Don't attempt a 64-bit pow2 division on PPC32
Hal Finkel
hfinkel at anl.gov
Tue Dec 23 00:38:50 PST 2014
Author: hfinkel
Date: Tue Dec 23 02:38:50 2014
New Revision: 224758
URL: http://llvm.org/viewvc/llvm-project?rev=224758&view=rev
Log:
[PowerPC] Don't attempt a 64-bit pow2 division on PPC32
In r224033, in moving the signed power-of-2 division expansion into
BuildSDIVPow2, I accidentally made it possible to attempt the lowering for a
64-bit division on PPC32. This later asserts.
Fixes PR21928.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/test/CodeGen/PowerPC/sdiv-pow2.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=224758&r1=224757&r2=224758&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Dec 23 02:38:50 2014
@@ -8966,6 +8966,8 @@ PPCTargetLowering::BuildSDIVPow2(SDNode
std::vector<SDNode *> *Created) const {
// fold (sdiv X, pow2)
EVT VT = N->getValueType(0);
+ if (VT == MVT::i64 && !Subtarget.isPPC64())
+ return SDValue();
if ((VT != MVT::i32 && VT != MVT::i64) ||
!(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
return SDValue();
Modified: llvm/trunk/test/CodeGen/PowerPC/sdiv-pow2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/sdiv-pow2.ll?rev=224758&r1=224757&r2=224758&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/sdiv-pow2.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/sdiv-pow2.ll Tue Dec 23 02:38:50 2014
@@ -1,4 +1,5 @@
; RUN: llc -mcpu=ppc64 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s | FileCheck -check-prefix=CHECK-32 %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
@@ -25,6 +26,10 @@ entry:
; CHECK: sradi [[REG1:[0-9]+]], 3, 3
; CHECK: addze 3, [[REG1]]
; CHECK: blr
+
+; CHECK-32-LABEL @foo8
+; CHECK-32-NOT: sradi
+; CHECK-32: blr
}
; Function Attrs: nounwind readnone
@@ -52,6 +57,10 @@ entry:
; CHECK: addze [[REG2:[0-9]+]], [[REG1]]
; CHECK: neg 3, [[REG2]]
; CHECK: blr
+
+; CHECK-32-LABEL @foo8n
+; CHECK-32-NOT: sradi
+; CHECK-32: blr
}
attributes #0 = { nounwind readnone }
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