[PATCH] [AArch64] Multiply-Negate operation not lowered to mneg in AArch64
Karthik Bhat
kv.bhat at samsung.com
Mon Dec 22 02:10:39 PST 2014
Hi t.p.northover,
Hi All,
The below code-
int a,b,c;
void fn() {
c = -(a*b);
}
when compiled on AArch64 bit with -O3 generates the assembly as follows-
fn: // @fn
// BB#0:
adrp x8, a
adrp x9, b
ldr w8, [x8, :lo12:a]
ldr w9, [x9, :lo12:b]
neg w8, w8
mul w8, w9, w8
adrp x9, c
str w8, [x9, :lo12:c]
ret
the neg and mul operation can be combined to mneg in AArch64. Gcc combines the above to mneg instruction.
Added a patch in llvm to do the same.
Post patch the following assembly is generated-
fn: // @fn
// BB#0:
adrp x8, a
adrp x9, b
ldr w8, [x8, :lo12:a]
ldr w9, [x9, :lo12:b]
mneg w8, w8, w9
adrp x9, c
str w8, [x9, :lo12:c]
ret
Please let me know if this is good to commit.
Thanks and Regards
Karthik Bhat
REPOSITORY
rL LLVM
http://reviews.llvm.org/D6754
Files:
lib/Target/AArch64/AArch64InstrInfo.td
test/CodeGen/AArch64/dp-3source.ll
Index: lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- lib/Target/AArch64/AArch64InstrInfo.td
+++ lib/Target/AArch64/AArch64InstrInfo.td
@@ -657,6 +657,10 @@
(MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
(MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
+def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
+ (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
+def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
+ (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
} // AddedComplexity = 7
let AddedComplexity = 5 in {
Index: test/CodeGen/AArch64/dp-3source.ll
===================================================================
--- test/CodeGen/AArch64/dp-3source.ll
+++ test/CodeGen/AArch64/dp-3source.ll
@@ -161,3 +161,18 @@
; CHECK: umnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
ret i64 %res
}
+
+ at a = common global i32 0, align 4
+ at b = common global i32 0, align 4
+ at c = common global i32 0, align 4
+
+define void @test_mneg(){
+; CHECK-LABEL: test_mneg:
+ %1 = load i32* @a, align 4
+ %2 = load i32* @b, align 4
+ %3 = sub i32 0, %1
+ %4 = mul i32 %2, %3
+ store i32 %4, i32* @c, align 4
+; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
+ ret void
+}
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