[PATCH] [X86][SSE] psrl(w/d/q) and psll(w/d/q) bit shifts for SSE2

[Simon Pilgrim]

Updated patch based on Chandler's comments.

Replaced the custom isSequential predicate with isSequentialOrUndefInRange in both lowerVectorShuffleAsByteShift and lowerVectorShuffleAsBitShift.


REPOSITORY
  rL LLVM

http://reviews.llvm.org/D6649

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/combine-or.ll
  test/CodeGen/X86/vector-idiv.ll
  test/CodeGen/X86/vector-shuffle-128-v16.ll
  test/CodeGen/X86/vector-shuffle-128-v4.ll
  test/CodeGen/X86/vector-shuffle-128-v8.ll
  test/CodeGen/X86/vector-shuffle-256-v16.ll
  test/CodeGen/X86/vector-shuffle-256-v32.ll
  test/CodeGen/X86/vector-shuffle-256-v8.ll

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