[PATCH] [X86][SSE] psrl(w/d/q) and psll(w/d/q) bit shifts for SSE2

Simon Pilgrim llvm-dev at redking.me.uk
Wed Dec 17 11:04:48 PST 2014


Updated patch based on Chandler's comments.

Replaced the custom isSequential predicate with isSequentialOrUndefInRange in both lowerVectorShuffleAsByteShift and lowerVectorShuffleAsBitShift.


REPOSITORY
  rL LLVM

http://reviews.llvm.org/D6649

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/combine-or.ll
  test/CodeGen/X86/vector-idiv.ll
  test/CodeGen/X86/vector-shuffle-128-v16.ll
  test/CodeGen/X86/vector-shuffle-128-v4.ll
  test/CodeGen/X86/vector-shuffle-128-v8.ll
  test/CodeGen/X86/vector-shuffle-256-v16.ll
  test/CodeGen/X86/vector-shuffle-256-v32.ll
  test/CodeGen/X86/vector-shuffle-256-v8.ll

EMAIL PREFERENCES
  http://reviews.llvm.org/settings/panel/emailpreferences/
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D6649.17407.patch
Type: text/x-patch
Size: 45896 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20141217/cb88d73a/attachment.bin>


More information about the llvm-commits mailing list