[llvm] r224343 - [Hexagon] Adding saturate and swizzle instructions.

[Colin LeMahieu]

Author: colinl
Date: Tue Dec 16 10:27:17 2014
New Revision: 224343

URL: http://llvm.org/viewvc/llvm-project?rev=224343&view=rev
Log:
[Hexagon] Adding saturate and swizzle instructions.

Added:
    llvm/trunk/test/MC/Disassembler/Hexagon/xtype_perm.txt
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=224343&r1=224342&r2=224343&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Tue Dec 16 10:27:17 2014
@@ -2710,6 +2710,14 @@ class T_S2op_1 <string mnemonic, bits<4>
 class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp>
   : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>;
 
+let hasNewValue = 1 in
+class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
+  : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>;
+
+let hasNewValue = 1 in
+class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
+  : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
+
 // Sign extend word to doubleword
 let isCodeGenOnly = 0 in
 def A2_sxtw   : T_S2op_1_di <"sxtw", 0b01, 0b000>;
@@ -2720,6 +2728,20 @@ def: Pat <(i64 (sext I32:$src)), (A2_sxt
 // STYPE/ALU -
 //===----------------------------------------------------------------------===//
 
+
+// Swizzle the bytes of a word
+let isCodeGenOnly = 0 in
+def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>;
+
+// Saturate
+let Defs = [USR_OVF], isCodeGenOnly = 0 in {
+  def A2_sat   : T_S2op_1_id <"sat", 0b11, 0b000>;
+  def A2_satb  : T_S2op_1_ii <"satb", 0b11, 0b111>;
+  def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>;
+  def A2_sath  : T_S2op_1_ii <"sath", 0b11, 0b100>;
+  def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>;
+}
+
 //===----------------------------------------------------------------------===//
 // STYPE/BIT +
 //===----------------------------------------------------------------------===//

Added: llvm/trunk/test/MC/Disassembler/Hexagon/xtype_perm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/xtype_perm.txt?rev=224343&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/xtype_perm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/xtype_perm.txt Tue Dec 16 10:27:17 2014
@@ -0,0 +1,14 @@
+# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+
+0x11 0xc0 0xd4 0x88
+# CHECK: r17 = sat(r21:20)
+0x91 0xc0 0xd5 0x8c
+# CHECK: r17 = sath(r21)
+0xb1 0xc0 0xd5 0x8c
+# CHECK: r17 = satuh(r21)
+0xd1 0xc0 0xd5 0x8c
+# CHECK: r17 = satub(r21)
+0xf1 0xc0 0xd5 0x8c
+# CHECK: r17 = satb(r21)
+0xf1 0xc0 0x95 0x8c
+# CHECK: r17 = swiz(r21)