[llvm] r224255 - Silence more static analyzer warnings.
Aaron Ballman
aaron at aaronballman.com
Tue Dec 16 06:06:40 PST 2014
On Mon, Dec 15, 2014 at 1:48 PM, Michael Ilseman <milseman at apple.com> wrote:
> Author: milseman
> Date: Mon Dec 15 12:48:43 2014
> New Revision: 224255
>
> URL: http://llvm.org/viewvc/llvm-project?rev=224255&view=rev
> Log:
> Silence more static analyzer warnings.
>
> Add in definedness checks for shift operators, null checks when
> pointers are assumed by the code to be non-null, and explicit
> unreachables.
While these checks are good, they introduced new warnings. When doing
these type of fixes, please make sure you test locally with a
relatively high warning level turned on. I've fixed the latest batch
in r224337.
Thanks!
~Aaron
>
> Modified:
> llvm/trunk/include/llvm/ADT/BitVector.h
> llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
> llvm/trunk/include/llvm/Object/COFF.h
> llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
> llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
> llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
> llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> llvm/trunk/lib/DebugInfo/DWARFDebugInfoEntry.cpp
> llvm/trunk/lib/Object/IRObjectFile.cpp
> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>
> Modified: llvm/trunk/include/llvm/ADT/BitVector.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/BitVector.h?rev=224255&r1=224254&r2=224255&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/ADT/BitVector.h (original)
> +++ llvm/trunk/include/llvm/ADT/BitVector.h Mon Dec 15 12:48:43 2014
> @@ -239,6 +239,7 @@ public:
> }
>
> BitVector &set(unsigned Idx) {
> + assert(Bits && "Bits never allocated");
> Bits[Idx / BITWORD_SIZE] |= BitWord(1) << (Idx % BITWORD_SIZE);
> return *this;
> }
> @@ -546,6 +547,7 @@ private:
>
> void grow(unsigned NewSize) {
> Capacity = std::max(NumBitWords(NewSize), Capacity * 2);
> + assert(Capacity > 0 && "realloc-ing zero space");
> Bits = (BitWord *)std::realloc(Bits, Capacity * sizeof(BitWord));
>
> clear_unused_bits();
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=224255&r1=224254&r2=224255&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Dec 15 12:48:43 2014
> @@ -768,6 +768,7 @@ protected:
> assert(NumValues == VTs.NumVTs &&
> "NumValues wasn't wide enough for its operands!");
> for (unsigned i = 0; i != Ops.size(); ++i) {
> + assert(OperandList && "no operands available");
> OperandList[i].setUser(this);
> OperandList[i].setInitial(Ops[i]);
> }
>
> Modified: llvm/trunk/include/llvm/Object/COFF.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/COFF.h?rev=224255&r1=224254&r2=224255&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Object/COFF.h (original)
> +++ llvm/trunk/include/llvm/Object/COFF.h Mon Dec 15 12:48:43 2014
> @@ -276,12 +276,14 @@ public:
> }
>
> const StringTableOffset &getStringTableOffset() const {
> + assert(isSet() && "COFFSymbolRef points to nothing!");
> return CS16 ? CS16->Name.Offset : CS32->Name.Offset;
> }
>
> uint32_t getValue() const { return CS16 ? CS16->Value : CS32->Value; }
>
> int32_t getSectionNumber() const {
> + assert(isSet() && "COFFSymbolRef points to nothing!");
> if (CS16) {
> // Reserved sections are returned as negative numbers.
> if (CS16->SectionNumber <= COFF::MaxNumberOfSections16)
> @@ -291,13 +293,18 @@ public:
> return static_cast<int32_t>(CS32->SectionNumber);
> }
>
> - uint16_t getType() const { return CS16 ? CS16->Type : CS32->Type; }
> + uint16_t getType() const {
> + assert(isSet() && "COFFSymbolRef points to nothing!");
> + return CS16 ? CS16->Type : CS32->Type;
> + }
>
> uint8_t getStorageClass() const {
> + assert(isSet() && "COFFSymbolRef points to nothing!");
> return CS16 ? CS16->StorageClass : CS32->StorageClass;
> }
>
> uint8_t getNumberOfAuxSymbols() const {
> + assert(isSet() && "COFFSymbolRef points to nothing!");
> return CS16 ? CS16->NumberOfAuxSymbols : CS32->NumberOfAuxSymbols;
> }
>
> @@ -360,6 +367,8 @@ public:
> }
>
> private:
> + bool isSet() const { return CS16 || CS32; }
> +
> const coff_symbol16 *CS16;
> const coff_symbol32 *CS32;
> };
>
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=224255&r1=224254&r2=224255&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Mon Dec 15 12:48:43 2014
> @@ -1492,10 +1492,12 @@ void AsmPrinter::EmitAlignment(unsigned
>
> if (NumBits == 0) return; // 1-byte aligned: no need to emit alignment.
>
> + assert(NumBits < std::numeric_limits<unsigned>::digits &&
> + "undefined behavior");
> if (getCurrentSection()->getKind().isText())
> - OutStreamer.EmitCodeAlignment(1 << NumBits);
> + OutStreamer.EmitCodeAlignment(1u << NumBits);
> else
> - OutStreamer.EmitValueToAlignment(1 << NumBits);
> + OutStreamer.EmitValueToAlignment(1u << NumBits);
> }
>
> //===----------------------------------------------------------------------===//
>
> Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=224255&r1=224254&r2=224255&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original)
> +++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Mon Dec 15 12:48:43 2014
> @@ -74,6 +74,8 @@ struct DomainValue {
>
> // Is domain available?
> bool hasDomain(unsigned domain) const {
> + assert(domain < std::numeric_limits<unsigned>::digits &&
> + "undefined behavior");
> return AvailableDomains & (1u << domain);
> }
>
> @@ -338,9 +340,11 @@ bool ExeDepsFix::merge(DomainValue *A, D
> // All uses of B are referred to A.
> B->Next = retain(A);
>
> - for (unsigned rx = 0; rx != NumRegs; ++rx)
> + for (unsigned rx = 0; rx != NumRegs; ++rx) {
> + assert(LiveRegs && "no space allocated for live registers");
> if (LiveRegs[rx].Value == B)
> setLiveReg(rx, A);
> + }
> return true;
> }
>
> @@ -645,6 +649,7 @@ void ExeDepsFix::visitSoftInstr(MachineI
> SmallVector<LiveReg, 4> Regs;
> for (SmallVectorImpl<int>::iterator i=used.begin(), e=used.end(); i!=e; ++i) {
> int rx = *i;
> + assert(LiveRegs && "no space allocated for live registers");
> const LiveReg &LR = LiveRegs[rx];
> // This useless DomainValue could have been missed above.
> if (!LR.Value->getCommonDomains(available)) {
> @@ -684,9 +689,11 @@ void ExeDepsFix::visitSoftInstr(MachineI
> continue;
>
> // If latest didn't merge, it is useless now. Kill all registers using it.
> - for (SmallVectorImpl<int>::iterator i=used.begin(), e=used.end(); i!=e; ++i)
> - if (LiveRegs[*i].Value == Latest)
> - kill(*i);
> + for (int i : used) {
> + assert(LiveRegs && "no space allocated for live registers");
> + if (LiveRegs[i].Value == Latest)
> + kill(i);
> + }
> }
>
> // dv is the DomainValue we are going to use for this instruction.
>
> Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=224255&r1=224254&r2=224255&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Mon Dec 15 12:48:43 2014
> @@ -129,6 +129,7 @@ void MachineRegisterInfo::verifyUseList(
> << " use list MachineOperand " << MO
> << " has no parent instruction.\n";
> Valid = false;
> + continue;
> }
> MachineOperand *MO0 = &MI->getOperand(0);
> unsigned NumOps = MI->getNumOperands();
>
> Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp?rev=224255&r1=224254&r2=224255&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Mon Dec 15 12:48:43 2014
> @@ -47,6 +47,7 @@ void RegisterClassInfo::runOnMachineFunc
> }
>
> // Does this MF have different CSRs?
> + assert(TRI && "no register info set");
> const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
> if (Update || CSR != CalleeSaved) {
> // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
> @@ -76,6 +77,7 @@ void RegisterClassInfo::runOnMachineFunc
> /// registers filtered out. Volatile registers come first followed by CSR
> /// aliases ordered according to the CSR order specified by the target.
> void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
> + assert(RC && "no register class given");
> RCInfo &RCI = RegClass[RC->getID()];
>
> // Raw register count, including all reserved regs.
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=224255&r1=224254&r2=224255&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Dec 15 12:48:43 2014
> @@ -566,6 +566,7 @@ static void getCopyToPartsVector(Selecti
> } else if (NumParts > 0) {
> // If the intermediate type was expanded, split each the value into
> // legal parts.
> + assert(NumIntermediates != 0 && "division by zero");
> assert(NumParts % NumIntermediates == 0 &&
> "Must expand into a divisible number of parts!");
> unsigned Factor = NumParts / NumIntermediates;
> @@ -1408,7 +1409,7 @@ SelectionDAGBuilder::EmitBranchForMerged
> if (TM.Options.NoNaNsFPMath)
> Condition = getFCmpCodeWithoutNaN(Condition);
> } else {
> - Condition = ISD::SETEQ; // silence warning.
> + (void)Condition; // silence warning.
> llvm_unreachable("Unknown compare instruction");
> }
>
>
> Modified: llvm/trunk/lib/DebugInfo/DWARFDebugInfoEntry.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/DebugInfo/DWARFDebugInfoEntry.cpp?rev=224255&r1=224254&r2=224255&view=diff
> ==============================================================================
> --- llvm/trunk/lib/DebugInfo/DWARFDebugInfoEntry.cpp (original)
> +++ llvm/trunk/lib/DebugInfo/DWARFDebugInfoEntry.cpp Mon Dec 15 12:48:43 2014
> @@ -76,7 +76,9 @@ void DWARFDebugInfoEntryMinimal::dump(ra
> static void dumpApplePropertyAttribute(raw_ostream &OS, uint64_t Val) {
> OS << " (";
> do {
> - uint64_t Bit = 1ULL << countTrailingZeros(Val);
> + uint64_t Shift = countTrailingZeros(Val);
> + assert(Shift < 64 && "undefined behavior");
> + uint64_t Bit = 1ULL << Shift;
> if (const char *PropName = ApplePropertyString(Bit))
> OS << PropName;
> else
>
> Modified: llvm/trunk/lib/Object/IRObjectFile.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/IRObjectFile.cpp?rev=224255&r1=224254&r2=224255&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Object/IRObjectFile.cpp (original)
> +++ llvm/trunk/lib/Object/IRObjectFile.cpp Mon Dec 15 12:48:43 2014
> @@ -181,6 +181,8 @@ void IRObjectFile::moveSymbolNext(DataRe
> Res = (Index << 2) | 3;
> break;
> }
> + default:
> + llvm_unreachable("unreachable case");
> }
>
> Symb.p = Res;
>
> Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h?rev=224255&r1=224254&r2=224255&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h (original)
> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h Mon Dec 15 12:48:43 2014
> @@ -236,6 +236,7 @@ static inline bool processLogicalImmedia
>
> if (isShiftedMask_64(Imm)) {
> I = countTrailingZeros(Imm);
> + assert(I < 64 && "undefined behavior");
> CTO = CountTrailingOnes_64(Imm >> I);
> } else {
> Imm |= ~Mask;
>
> Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp?rev=224255&r1=224254&r2=224255&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp Mon Dec 15 12:48:43 2014
> @@ -177,7 +177,9 @@ private:
> MCELF::SetType(SD, ELF::STT_NOTYPE);
> MCELF::SetBinding(SD, ELF::STB_LOCAL);
> SD.setExternal(false);
> - Symbol->setSection(*getCurrentSection().first);
> + auto Sec = getCurrentSection().first;
> + assert(Sec && "need a section");
> + Symbol->setSection(*Sec);
>
> const MCExpr *Value = MCSymbolRefExpr::Create(Start, getContext());
> Symbol->setVariableValue(Value);
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=224255&r1=224254&r2=224255&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Dec 15 12:48:43 2014
> @@ -8577,7 +8577,9 @@ static SDValue PerformBFICombine(SDNode
> unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
> unsigned LSB = countTrailingZeros(~InvMask);
> unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
> - unsigned Mask = (1 << Width)-1;
> + assert(Width < std::numeric_limits<unsigned>::digits &&
> + "undefined behavior");
> + unsigned Mask = (1u << Width) - 1;
> unsigned Mask2 = N11C->getZExtValue();
> if ((Mask & (~Mask2)) == 0)
> return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
>
>
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