[PATCH] [X86][SSE] psrl(w/d/q) and psll(w/d/q) bit shifts for SSE2

[Simon Pilgrim]

Hi chandlerc, qcolombet, andreadb,

Patch to match cases where shuffle masks can be reduced to bit shifts. Similar to byte shift shuffle matching from D5699.

For integer vector shuffles where lanes are being moved to the left/right in short groups and zeros are being inserted. Each integer type can be shifted safely using any wider type (so i8 -> i16/i32/i64, i16 -> i32/i64, i32 -> i64).

I have an upcoming patch that will fix the combine-or.ll domain mismatch.

I kept to just providing the immediate versions of the SSE2 logical bit shifts - there may be a case for adding support for AVX2 per-lane shifts but I don't have the hardware to test this.

Theoretically I think in the future this could be generalised (endian fixes) and moved to DAGCombine?

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D6649

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/combine-or.ll
  test/CodeGen/X86/vector-idiv.ll
  test/CodeGen/X86/vector-shuffle-128-v16.ll
  test/CodeGen/X86/vector-shuffle-128-v4.ll
  test/CodeGen/X86/vector-shuffle-128-v8.ll
  test/CodeGen/X86/vector-shuffle-256-v16.ll
  test/CodeGen/X86/vector-shuffle-256-v32.ll
  test/CodeGen/X86/vector-shuffle-256-v8.ll

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