[llvm] r224042 - [CodeGen] Add print and verify pass after each MachineFunctionPass by default
Rafael Espíndola
rafael.espindola at gmail.com
Thu Dec 11 12:09:39 PST 2014
sorry, I reverted this and r224043 as check-all was failing on linux.
On 11 December 2014 at 14:42, Matthias Braun <matze at braunis.de> wrote:
> Author: matze
> Date: Thu Dec 11 13:42:05 2014
> New Revision: 224042
>
> URL: http://llvm.org/viewvc/llvm-project?rev=224042&view=rev
> Log:
> [CodeGen] Add print and verify pass after each MachineFunctionPass by default
>
> Previously print+verify passes were added in a very unsystematic way, which is
> annoying when debugging as you miss intermediate steps and allows bugs to stay
> unnotice when no verification is performed.
>
> To make this change practical I added the possibility to explicitely disable
> verification. I used this option on all places where no verification was
> performed previously (because alot of places actually don't pass the
> MachineVerifier).
> In the long term these problems should be fixed properly and verification
> enabled after each pass. I'll enable some more verification in subsequent
> commits.
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/Passes.h
> llvm/trunk/lib/CodeGen/Passes.cpp
> llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
> llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
> llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp
> llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
> llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp
> llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
> llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp
> llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
> llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp
> llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
> llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/Passes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=224042&r1=224041&r2=224042&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/Passes.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/Passes.h Thu Dec 11 13:42:05 2014
> @@ -105,6 +105,7 @@ private:
> AnalysisID StopAfter;
> bool Started;
> bool Stopped;
> + bool AddingMachinePasses;
>
> protected:
> TargetMachine *TM;
> @@ -259,12 +260,9 @@ protected:
> return false;
> }
>
> - /// addPreRegAlloc - This method may be implemented by targets that want to
> - /// run passes immediately before register allocation. This should return
> - /// true if -print-machineinstrs should print after these passes.
> - virtual bool addPreRegAlloc() {
> - return false;
> - }
> + /// This method may be implemented by targets that want to run passes
> + /// immediately before register allocation.
> + virtual void addPreRegAlloc() { }
>
> /// createTargetRegisterAllocator - Create the register allocator pass for
> /// this target at the current optimization level.
> @@ -290,24 +288,16 @@ protected:
> return false;
> }
>
> - /// addPostRegAlloc - This method may be implemented by targets that want to
> - /// run passes after register allocation pass pipeline but before
> - /// prolog-epilog insertion. This should return true if -print-machineinstrs
> - /// should print after these passes.
> - virtual bool addPostRegAlloc() {
> - return false;
> - }
> + /// This method may be implemented by targets that want to run passes after
> + /// register allocation pass pipeline but before prolog-epilog insertion.
> + virtual void addPostRegAlloc() { }
>
> /// Add passes that optimize machine instructions after register allocation.
> virtual void addMachineLateOptimization();
>
> - /// addPreSched2 - This method may be implemented by targets that want to
> - /// run passes after prolog-epilog insertion and before the second instruction
> - /// scheduling pass. This should return true if -print-machineinstrs should
> - /// print after these passes.
> - virtual bool addPreSched2() {
> - return false;
> - }
> + /// This method may be implemented by targets that want to run passes after
> + /// prolog-epilog insertion and before the second instruction scheduling pass.
> + virtual void addPreSched2() { }
>
> /// addGCPasses - Add late codegen passes that analyze code for garbage
> /// collection. This should return true if GC info should be printed after
> @@ -317,24 +307,30 @@ protected:
> /// Add standard basic block placement passes.
> virtual void addBlockPlacement();
>
> - /// addPreEmitPass - This pass may be implemented by targets that want to run
> - /// passes immediately before machine code is emitted. This should return
> - /// true if -print-machineinstrs should print out the code after the passes.
> - virtual bool addPreEmitPass() {
> - return false;
> - }
> + /// This pass may be implemented by targets that want to run passes
> + /// immediately before machine code is emitted.
> + virtual void addPreEmitPass() { }
>
> /// Utilities for targets to add passes to the pass manager.
> ///
>
> /// Add a CodeGen pass at this point in the pipeline after checking overrides.
> /// Return the pass that was added, or zero if no pass was added.
> - AnalysisID addPass(AnalysisID PassID);
> + /// @p printAfter if true and adding a machine function pass add an extra
> + /// machine printer pass afterwards
> + /// @p verifyAfter if true and adding a machine function pass add an extra
> + /// machine verification pass afterwards.
> + AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
> + bool printAfter = true);
>
> /// Add a pass to the PassManager if that pass is supposed to be run, as
> /// determined by the StartAfter and StopAfter options. Takes ownership of the
> /// pass.
> - void addPass(Pass *P);
> + /// @p printAfter if true and adding a machine function pass add an extra
> + /// machine printer pass afterwards
> + /// @p verifyAfter if true and adding a machine function pass add an extra
> + /// machine verification pass afterwards.
> + void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
>
> /// addMachinePasses helper to create the target-selected or overriden
> /// regalloc pass.
> @@ -343,7 +339,14 @@ protected:
> /// printAndVerify - Add a pass to dump then verify the machine function, if
> /// those steps are enabled.
> ///
> - void printAndVerify(const char *Banner);
> + void printAndVerify(const std::string &Banner);
> +
> + /// Add a pass to print the machine function if printing is enabled.
> + void addPrintPass(const std::string &Banner);
> +
> + /// Add a pass to perform basic verification of the machine function if
> + /// verification is enabled.
> + void addVerifyPass(const std::string &Banner);
> };
> } // namespace llvm
>
>
> Modified: llvm/trunk/lib/CodeGen/Passes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Passes.cpp?rev=224042&r1=224041&r2=224042&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/Passes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/Passes.cpp Thu Dec 11 13:42:05 2014
> @@ -235,8 +235,8 @@ TargetPassConfig::~TargetPassConfig() {
> // registers all common codegen passes.
> TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
> : ImmutablePass(ID), PM(&pm), StartAfter(nullptr), StopAfter(nullptr),
> - Started(true), Stopped(false), TM(tm), Impl(nullptr), Initialized(false),
> - DisableVerify(false),
> + Started(true), Stopped(false), AddingMachinePasses(false), TM(tm),
> + Impl(nullptr), Initialized(false), DisableVerify(false),
> EnableTailMerge(true) {
>
> Impl = new PassConfigImpl();
> @@ -304,7 +304,7 @@ IdentifyingPassPtr TargetPassConfig::get
> /// a later pass or that it should stop after an earlier pass, then do not add
> /// the pass. Finally, compare the current pass against the StartAfter
> /// and StopAfter options and change the Started/Stopped flags accordingly.
> -void TargetPassConfig::addPass(Pass *P) {
> +void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
> assert(!Initialized && "PassConfig is immutable");
>
> // Cache the Pass ID here in case the pass manager finds this pass is
> @@ -313,10 +313,18 @@ void TargetPassConfig::addPass(Pass *P)
> // and shouldn't reference it.
> AnalysisID PassID = P->getPassID();
>
> - if (Started && !Stopped)
> + if (Started && !Stopped) {
> PM->add(P);
> - else
> + if (AddingMachinePasses) {
> + std::string Banner = std::string("After ")+std::string(P->getPassName());
> + if (printAfter)
> + addPrintPass(Banner);
> + if (verifyAfter)
> + addVerifyPass(Banner);
> + }
> + } else {
> delete P;
> + }
> if (StopAfter == PassID)
> Stopped = true;
> if (StartAfter == PassID)
> @@ -330,7 +338,8 @@ void TargetPassConfig::addPass(Pass *P)
> ///
> /// addPass cannot return a pointer to the pass instance because is internal the
> /// PassManager and the instance we create here may already be freed.
> -AnalysisID TargetPassConfig::addPass(AnalysisID PassID) {
> +AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
> + bool printAfter) {
> IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
> IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
> if (!FinalPtr.isValid())
> @@ -345,7 +354,7 @@ AnalysisID TargetPassConfig::addPass(Ana
> llvm_unreachable("Pass ID not registered");
> }
> AnalysisID FinalID = P->getPassID();
> - addPass(P); // Ends the lifetime of P.
> + addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
>
> // Add the passes after the pass P if there is any.
> for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator
> @@ -360,18 +369,25 @@ AnalysisID TargetPassConfig::addPass(Ana
> NP = Pass::createPass((*I).second.getID());
> assert(NP && "Pass ID not registered");
> }
> - addPass(NP);
> + addPass(NP, false, false);
> }
> }
> return FinalID;
> }
>
> -void TargetPassConfig::printAndVerify(const char *Banner) {
> +void TargetPassConfig::printAndVerify(const std::string &Banner) {
> + addPrintPass(Banner);
> + addVerifyPass(Banner);
> +}
> +
> +void TargetPassConfig::addPrintPass(const std::string &Banner) {
> if (TM->shouldPrintMachineCode())
> - addPass(createMachineFunctionPrinterPass(dbgs(), Banner));
> + PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
> +}
>
> +void TargetPassConfig::addVerifyPass(const std::string &Banner) {
> if (VerifyMachineCode)
> - addPass(createMachineVerifierPass(Banner));
> + PM->add(createMachineVerifierPass(Banner));
> }
>
> /// Add common target configurable passes that perform LLVM IR to IR transforms
> @@ -491,6 +507,8 @@ void TargetPassConfig::addISelPrepare()
> /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
> /// before/after any target-independent pass. But it's currently overkill.
> void TargetPassConfig::addMachinePasses() {
> + AddingMachinePasses = true;
> +
> // Insert a machine instr printer pass after the specified pass.
> // If -print-machineinstrs specified, print machineinstrs after all passes.
> if (StringRef(PrintMachineInstrs.getValue()).equals(""))
> @@ -510,8 +528,7 @@ void TargetPassConfig::addMachinePasses(
> printAndVerify("After Instruction Selection");
>
> // Expand pseudo-instructions emitted by ISel.
> - if (addPass(&ExpandISelPseudosID))
> - printAndVerify("After ExpandISelPseudos");
> + addPass(&ExpandISelPseudosID);
>
> // Add passes that optimize machine instructions in SSA form.
> if (getOptLevel() != CodeGenOpt::None) {
> @@ -519,12 +536,11 @@ void TargetPassConfig::addMachinePasses(
> } else {
> // If the target requests it, assign local variables to stack slots relative
> // to one another and simplify frame index references where possible.
> - addPass(&LocalStackSlotAllocationID);
> + addPass(&LocalStackSlotAllocationID, false);
> }
>
> // Run pre-ra passes.
> - if (addPreRegAlloc())
> - printAndVerify("After PreRegAlloc passes");
> + addPreRegAlloc();
>
> // Run register allocation and passes that are tightly coupled with it,
> // including phi elimination and scheduling.
> @@ -534,12 +550,10 @@ void TargetPassConfig::addMachinePasses(
> addFastRegAlloc(createRegAllocPass(false));
>
> // Run post-ra passes.
> - if (addPostRegAlloc())
> - printAndVerify("After PostRegAlloc passes");
> + addPostRegAlloc();
>
> // Insert prolog/epilog code. Eliminate abstract frame index references...
> addPass(&PrologEpilogCodeInserterID);
> - printAndVerify("After PrologEpilogCodeInserter");
>
> /// Add passes that optimize machine instructions after register allocation.
> if (getOptLevel() != CodeGenOpt::None)
> @@ -547,11 +561,9 @@ void TargetPassConfig::addMachinePasses(
>
> // Expand pseudo instructions before second scheduling pass.
> addPass(&ExpandPostRAPseudosID);
> - printAndVerify("After ExpandPostRAPseudos");
>
> // Run pre-sched2 passes.
> - if (addPreSched2())
> - printAndVerify("After PreSched2 passes");
> + addPreSched2();
>
> // Second pass scheduler.
> if (getOptLevel() != CodeGenOpt::None) {
> @@ -559,66 +571,61 @@ void TargetPassConfig::addMachinePasses(
> addPass(&PostMachineSchedulerID);
> else
> addPass(&PostRASchedulerID);
> - printAndVerify("After PostRAScheduler");
> }
>
> // GC
> if (addGCPasses()) {
> if (PrintGCInfo)
> - addPass(createGCInfoPrinter(dbgs()));
> + addPass(createGCInfoPrinter(dbgs()), false, false);
> }
>
> // Basic block placement.
> if (getOptLevel() != CodeGenOpt::None)
> addBlockPlacement();
>
> - if (addPreEmitPass())
> - printAndVerify("After PreEmit passes");
> + addPreEmitPass();
> +
> + addPass(&StackMapLivenessID, false);
>
> - addPass(&StackMapLivenessID);
> + AddingMachinePasses = false;
> }
>
> /// Add passes that optimize machine instructions in SSA form.
> void TargetPassConfig::addMachineSSAOptimization() {
> // Pre-ra tail duplication.
> - if (addPass(&EarlyTailDuplicateID))
> - printAndVerify("After Pre-RegAlloc TailDuplicate");
> + addPass(&EarlyTailDuplicateID);
>
> // Optimize PHIs before DCE: removing dead PHI cycles may make more
> // instructions dead.
> - addPass(&OptimizePHIsID);
> + addPass(&OptimizePHIsID, false);
>
> // This pass merges large allocas. StackSlotColoring is a different pass
> // which merges spill slots.
> - addPass(&StackColoringID);
> + addPass(&StackColoringID, false);
>
> // If the target requests it, assign local variables to stack slots relative
> // to one another and simplify frame index references where possible.
> - addPass(&LocalStackSlotAllocationID);
> + addPass(&LocalStackSlotAllocationID, false);
>
> // With optimization, dead code should already be eliminated. However
> // there is one known exception: lowered code for arguments that are only
> // used by tail calls, where the tail calls reuse the incoming stack
> // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
> addPass(&DeadMachineInstructionElimID);
> - printAndVerify("After codegen DCE pass");
>
> // Allow targets to insert passes that improve instruction level parallelism,
> // like if-conversion. Such passes will typically need dominator trees and
> // loop info, just like LICM and CSE below.
> - if (addILPOpts())
> - printAndVerify("After ILP optimizations");
> + addILPOpts();
>
> - addPass(&MachineLICMID);
> - addPass(&MachineCSEID);
> + addPass(&MachineLICMID, false);
> + addPass(&MachineCSEID, false);
> addPass(&MachineSinkingID);
> - printAndVerify("After Machine LICM, CSE and Sinking passes");
>
> - addPass(&PeepholeOptimizerID);
> + addPass(&PeepholeOptimizerID, false);
> // Clean-up the dead code that may have been generated by peephole
> // rewriting.
> addPass(&DeadMachineInstructionElimID);
> - printAndVerify("After codegen peephole optimization pass");
> }
>
> //===---------------------------------------------------------------------===//
> @@ -701,18 +708,17 @@ bool TargetPassConfig::usingDefaultRegAl
> /// Add the minimum set of target-independent passes that are required for
> /// register allocation. No coalescing or scheduling.
> void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
> - addPass(&PHIEliminationID);
> - addPass(&TwoAddressInstructionPassID);
> + addPass(&PHIEliminationID, false);
> + addPass(&TwoAddressInstructionPassID, false);
>
> addPass(RegAllocPass);
> - printAndVerify("After Register Allocation");
> }
>
> /// Add standard target-independent passes that are tightly coupled with
> /// optimized register allocation, including coalescing, machine instruction
> /// scheduling, and register allocation itself.
> void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
> - addPass(&ProcessImplicitDefsID);
> + addPass(&ProcessImplicitDefsID, false);
>
> // LiveVariables currently requires pure SSA form.
> //
> @@ -720,35 +726,30 @@ void TargetPassConfig::addOptimizedRegAl
> // LiveVariables can be removed completely, and LiveIntervals can be directly
> // computed. (We still either need to regenerate kill flags after regalloc, or
> // preferably fix the scavenger to not depend on them).
> - addPass(&LiveVariablesID);
> + addPass(&LiveVariablesID, false);
>
> // Edge splitting is smarter with machine loop info.
> - addPass(&MachineLoopInfoID);
> - addPass(&PHIEliminationID);
> + addPass(&MachineLoopInfoID, false);
> + addPass(&PHIEliminationID, false);
>
> // Eventually, we want to run LiveIntervals before PHI elimination.
> if (EarlyLiveIntervals)
> - addPass(&LiveIntervalsID);
> + addPass(&LiveIntervalsID, false);
>
> - addPass(&TwoAddressInstructionPassID);
> + addPass(&TwoAddressInstructionPassID, false);
> addPass(&RegisterCoalescerID);
> - printAndVerify("After Register Coalescing");
>
> // PreRA instruction scheduling.
> - if (addPass(&MachineSchedulerID))
> - printAndVerify("After Machine Scheduling");
> + addPass(&MachineSchedulerID);
>
> // Add the selected register allocation pass.
> addPass(RegAllocPass);
> - printAndVerify("After Register Allocation, before rewriter");
>
> // Allow targets to change the register assignments before rewriting.
> - if (addPreRewrite())
> - printAndVerify("After pre-rewrite passes");
> + addPreRewrite();
>
> // Finally rewrite virtual registers.
> addPass(&VirtRegRewriterID);
> - printAndVerify("After Virtual Register Rewriter");
>
> // Perform stack slot coloring and post-ra machine LICM.
> //
> @@ -760,8 +761,6 @@ void TargetPassConfig::addOptimizedRegAl
> //
> // FIXME: can this move into MachineLateOptimization?
> addPass(&PostRAMachineLICMID);
> -
> - printAndVerify("After StackSlotColoring and postra Machine LICM");
> }
>
> //===---------------------------------------------------------------------===//
> @@ -771,34 +770,30 @@ void TargetPassConfig::addOptimizedRegAl
> /// Add passes that optimize machine instructions after register allocation.
> void TargetPassConfig::addMachineLateOptimization() {
> // Branch folding must be run after regalloc and prolog/epilog insertion.
> - if (addPass(&BranchFolderPassID))
> - printAndVerify("After BranchFolding");
> + addPass(&BranchFolderPassID);
>
> // Tail duplication.
> // Note that duplicating tail just increases code size and degrades
> // performance for targets that require Structured Control Flow.
> // In addition it can also make CFG irreducible. Thus we disable it.
> - if (!TM->requiresStructuredCFG() && addPass(&TailDuplicateID))
> - printAndVerify("After TailDuplicate");
> + if (!TM->requiresStructuredCFG())
> + addPass(&TailDuplicateID);
>
> // Copy propagation.
> - if (addPass(&MachineCopyPropagationID))
> - printAndVerify("After copy propagation pass");
> + addPass(&MachineCopyPropagationID);
> }
>
> /// Add standard GC passes.
> bool TargetPassConfig::addGCPasses() {
> - addPass(&GCMachineCodeAnalysisID);
> + addPass(&GCMachineCodeAnalysisID, false);
> return true;
> }
>
> /// Add standard basic block placement passes.
> void TargetPassConfig::addBlockPlacement() {
> - if (addPass(&MachineBlockPlacementID)) {
> + if (addPass(&MachineBlockPlacementID, false)) {
> // Run a separate pass to collect block placement statistics.
> if (EnableBlockPlacementStats)
> addPass(&MachineBlockPlacementStatsID);
> -
> - printAndVerify("After machine block placement.");
> }
> }
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=224042&r1=224041&r2=224042&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp Thu Dec 11 13:42:05 2014
> @@ -181,10 +181,10 @@ public:
> bool addPreISel() override;
> bool addInstSelector() override;
> bool addILPOpts() override;
> - bool addPreRegAlloc() override;
> - bool addPostRegAlloc() override;
> - bool addPreSched2() override;
> - bool addPreEmitPass() override;
> + void addPreRegAlloc() override;
> + void addPostRegAlloc() override;
> + void addPreSched2() override;
> + void addPreEmitPass() override;
> };
> } // namespace
>
> @@ -267,47 +267,43 @@ bool AArch64PassConfig::addILPOpts() {
> return true;
> }
>
> -bool AArch64PassConfig::addPreRegAlloc() {
> +void AArch64PassConfig::addPreRegAlloc() {
> // Use AdvSIMD scalar instructions whenever profitable.
> if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
> - addPass(createAArch64AdvSIMDScalar());
> + addPass(createAArch64AdvSIMDScalar(), false);
> // The AdvSIMD pass may produce copies that can be rewritten to
> // be register coaleascer friendly.
> addPass(&PeepholeOptimizerID);
> }
> - return true;
> }
>
> -bool AArch64PassConfig::addPostRegAlloc() {
> +void AArch64PassConfig::addPostRegAlloc() {
> // Change dead register definitions to refer to the zero register.
> if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
> - addPass(createAArch64DeadRegisterDefinitions());
> + addPass(createAArch64DeadRegisterDefinitions(), false);
> if (TM->getOptLevel() != CodeGenOpt::None &&
> (TM->getSubtarget<AArch64Subtarget>().isCortexA53() ||
> TM->getSubtarget<AArch64Subtarget>().isCortexA57()) &&
> usingDefaultRegAlloc())
> // Improve performance for some FP/SIMD code for A57.
> addPass(createAArch64A57FPLoadBalancing());
> - return true;
> }
>
> -bool AArch64PassConfig::addPreSched2() {
> +void AArch64PassConfig::addPreSched2() {
> // Expand some pseudo instructions to allow proper scheduling.
> - addPass(createAArch64ExpandPseudoPass());
> + addPass(createAArch64ExpandPseudoPass(), false);
> // Use load/store pair instructions when possible.
> if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
> addPass(createAArch64LoadStoreOptimizationPass());
> - return true;
> }
>
> -bool AArch64PassConfig::addPreEmitPass() {
> +void AArch64PassConfig::addPreEmitPass() {
> if (EnableA53Fix835769)
> - addPass(createAArch64A53Fix835769());
> + addPass(createAArch64A53Fix835769(), false);
> // Relax conditional branch instructions if they're otherwise out of
> // range of their destination.
> - addPass(createAArch64BranchRelaxation());
> + addPass(createAArch64BranchRelaxation(), false);
> if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
> TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
> addPass(createAArch64CollectLOHPass());
> - return true;
> }
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=224042&r1=224041&r2=224042&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Dec 11 13:42:05 2014
> @@ -197,9 +197,9 @@ public:
> void addIRPasses() override;
> bool addPreISel() override;
> bool addInstSelector() override;
> - bool addPreRegAlloc() override;
> - bool addPreSched2() override;
> - bool addPreEmitPass() override;
> + void addPreRegAlloc() override;
> + void addPreSched2() override;
> + void addPreEmitPass() override;
> };
> } // namespace
>
> @@ -241,59 +241,53 @@ bool ARMPassConfig::addInstSelector() {
> return false;
> }
>
> -bool ARMPassConfig::addPreRegAlloc() {
> +void ARMPassConfig::addPreRegAlloc() {
> if (getOptLevel() != CodeGenOpt::None)
> - addPass(createARMLoadStoreOptimizationPass(true));
> + addPass(createARMLoadStoreOptimizationPass(true), false);
> if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
> - addPass(createMLxExpansionPass());
> + addPass(createMLxExpansionPass(), false);
> // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
> // enabled when NEON is available.
> if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
> getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
> addPass(createA15SDOptimizerPass());
> }
> - return true;
> }
>
> -bool ARMPassConfig::addPreSched2() {
> +void ARMPassConfig::addPreSched2() {
> if (getOptLevel() != CodeGenOpt::None) {
> - addPass(createARMLoadStoreOptimizationPass());
> - printAndVerify("After ARM load / store optimizer");
> + addPass(createARMLoadStoreOptimizationPass(), false);
>
> if (getARMSubtarget().hasNEON())
> - addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
> + addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass), false);
> }
>
> // Expand some pseudo instructions into multiple instructions to allow
> // proper scheduling.
> - addPass(createARMExpandPseudoPass());
> + addPass(createARMExpandPseudoPass(), false);
>
> if (getOptLevel() != CodeGenOpt::None) {
> if (!getARMSubtarget().isThumb1Only()) {
> // in v8, IfConversion depends on Thumb instruction widths
> if (getARMSubtarget().restrictIT() &&
> !getARMSubtarget().prefers32BitThumb())
> - addPass(createThumb2SizeReductionPass());
> - addPass(&IfConverterID);
> + addPass(createThumb2SizeReductionPass(), false);
> + addPass(&IfConverterID, false);
> }
> }
> if (getARMSubtarget().isThumb2())
> addPass(createThumb2ITBlockPass());
> -
> - return true;
> }
>
> -bool ARMPassConfig::addPreEmitPass() {
> +void ARMPassConfig::addPreEmitPass() {
> if (getARMSubtarget().isThumb2()) {
> if (!getARMSubtarget().prefers32BitThumb())
> - addPass(createThumb2SizeReductionPass());
> + addPass(createThumb2SizeReductionPass(), false);
>
> // Constant island pass work on unbundled instructions.
> - addPass(&UnpackMachineBundlesID);
> + addPass(&UnpackMachineBundlesID, false);
> }
>
> - addPass(createARMOptimizeBarriersPass());
> + addPass(createARMOptimizeBarriersPass(), false);
> addPass(createARMConstantIslandPass());
> -
> - return true;
> }
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp?rev=224042&r1=224041&r2=224042&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp Thu Dec 11 13:42:05 2014
> @@ -103,10 +103,10 @@ public:
> }
>
> bool addInstSelector() override;
> - bool addPreRegAlloc() override;
> - bool addPostRegAlloc() override;
> - bool addPreSched2() override;
> - bool addPreEmitPass() override;
> + void addPreRegAlloc() override;
> + void addPostRegAlloc() override;
> + void addPreSched2() override;
> + void addPreEmitPass() override;
> };
> } // namespace
>
> @@ -131,51 +131,45 @@ bool HexagonPassConfig::addInstSelector(
> return false;
> }
>
> -bool HexagonPassConfig::addPreRegAlloc() {
> +void HexagonPassConfig::addPreRegAlloc() {
> if (getOptLevel() != CodeGenOpt::None)
> if (!DisableHardwareLoops)
> - addPass(createHexagonHardwareLoops());
> - return false;
> + addPass(createHexagonHardwareLoops(), false);
> }
>
> -bool HexagonPassConfig::addPostRegAlloc() {
> +void HexagonPassConfig::addPostRegAlloc() {
> const HexagonTargetMachine &TM = getHexagonTargetMachine();
> if (getOptLevel() != CodeGenOpt::None)
> if (!DisableHexagonCFGOpt)
> - addPass(createHexagonCFGOptimizer(TM));
> - return false;
> + addPass(createHexagonCFGOptimizer(TM), false);
> }
>
> -bool HexagonPassConfig::addPreSched2() {
> +void HexagonPassConfig::addPreSched2() {
> const HexagonTargetMachine &TM = getHexagonTargetMachine();
>
> - addPass(createHexagonCopyToCombine());
> + addPass(createHexagonCopyToCombine(), false);
> if (getOptLevel() != CodeGenOpt::None)
> - addPass(&IfConverterID);
> + addPass(&IfConverterID, false);
> addPass(createHexagonSplitConst32AndConst64(TM));
> - printAndVerify("After hexagon split const32/64 pass");
> - return true;
> }
>
> -bool HexagonPassConfig::addPreEmitPass() {
> +void HexagonPassConfig::addPreEmitPass() {
> const HexagonTargetMachine &TM = getHexagonTargetMachine();
> bool NoOpt = (getOptLevel() == CodeGenOpt::None);
>
> if (!NoOpt)
> - addPass(createHexagonNewValueJump());
> + addPass(createHexagonNewValueJump(), false);
>
> // Expand Spill code for predicate registers.
> - addPass(createHexagonExpandPredSpillCode(TM));
> + addPass(createHexagonExpandPredSpillCode(TM), false);
>
> // Split up TFRcondsets into conditional transfers.
> - addPass(createHexagonSplitTFRCondSets(TM));
> + addPass(createHexagonSplitTFRCondSets(TM), false);
>
> // Create Packets.
> if (!NoOpt) {
> if (!DisableHardwareLoops)
> - addPass(createHexagonFixupHwLoops());
> - addPass(createHexagonPacketizer());
> + addPass(createHexagonFixupHwLoops(), false);
> + addPass(createHexagonPacketizer(), false);
> }
> -
> - return false;
> }
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=224042&r1=224041&r2=224042&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Thu Dec 11 13:42:05 2014
> @@ -50,7 +50,7 @@ public:
> }
>
> bool addInstSelector() override;
> - bool addPreEmitPass() override;
> + void addPreEmitPass() override;
> };
> } // namespace
>
> @@ -64,8 +64,7 @@ bool MSP430PassConfig::addInstSelector()
> return false;
> }
>
> -bool MSP430PassConfig::addPreEmitPass() {
> +void MSP430PassConfig::addPreEmitPass() {
> // Must run branch selection immediately preceding the asm printer.
> - addPass(createMSP430BranchSelectionPass());
> - return false;
> + addPass(createMSP430BranchSelectionPass(), false);
> }
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=224042&r1=224041&r2=224042&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Thu Dec 11 13:42:05 2014
> @@ -170,9 +170,9 @@ public:
> void addIRPasses() override;
> bool addInstSelector() override;
> void addMachineSSAOptimization() override;
> - bool addPreEmitPass() override;
> + void addPreEmitPass() override;
>
> - bool addPreRegAlloc() override;
> + void addPreRegAlloc() override;
>
> };
> } // namespace
> @@ -203,13 +203,9 @@ void MipsPassConfig::addMachineSSAOptimi
> TargetPassConfig::addMachineSSAOptimization();
> }
>
> -bool MipsPassConfig::addPreRegAlloc() {
> - if (getOptLevel() == CodeGenOpt::None) {
> +void MipsPassConfig::addPreRegAlloc() {
> + if (getOptLevel() == CodeGenOpt::None)
> addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
> - return true;
> - }
> - else
> - return false;
> }
>
> void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
> @@ -228,10 +224,9 @@ void MipsTargetMachine::addAnalysisPasse
> // Implemented by targets that want to run passes immediately before
> // machine code is emitted. return true if -print-machineinstrs should
> // print out the code after the passes.
> -bool MipsPassConfig::addPreEmitPass() {
> +void MipsPassConfig::addPreEmitPass() {
> MipsTargetMachine &TM = getMipsTargetMachine();
> - addPass(createMipsDelaySlotFillerPass(TM));
> - addPass(createMipsLongBranchPass(TM));
> + addPass(createMipsDelaySlotFillerPass(TM), false);
> + addPass(createMipsLongBranchPass(TM), false);
> addPass(createMipsConstantIslandPass(TM));
> - return true;
> }
>
> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp?rev=224042&r1=224041&r2=224042&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp Thu Dec 11 13:42:05 2014
> @@ -110,8 +110,7 @@ public:
>
> void addIRPasses() override;
> bool addInstSelector() override;
> - bool addPreRegAlloc() override;
> - bool addPostRegAlloc() override;
> + void addPostRegAlloc() override;
> void addMachineSSAOptimization() override;
>
> FunctionPass *createTargetRegisterAllocator(bool) override;
> @@ -183,10 +182,8 @@ bool NVPTXPassConfig::addInstSelector()
> return false;
> }
>
> -bool NVPTXPassConfig::addPreRegAlloc() { return false; }
> -bool NVPTXPassConfig::addPostRegAlloc() {
> - addPass(createNVPTXPrologEpilogPass());
> - return false;
> +void NVPTXPassConfig::addPostRegAlloc() {
> + addPass(createNVPTXPrologEpilogPass(), false);
> }
>
> FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=224042&r1=224041&r2=224042&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Thu Dec 11 13:42:05 2014
> @@ -162,9 +162,9 @@ public:
> bool addPreISel() override;
> bool addILPOpts() override;
> bool addInstSelector() override;
> - bool addPreRegAlloc() override;
> - bool addPreSched2() override;
> - bool addPreEmitPass() override;
> + void addPreRegAlloc() override;
> + void addPreSched2() override;
> + void addPreEmitPass() override;
> };
> } // namespace
>
> @@ -216,28 +216,24 @@ bool PPCPassConfig::addInstSelector() {
> return false;
> }
>
> -bool PPCPassConfig::addPreRegAlloc() {
> +void PPCPassConfig::addPreRegAlloc() {
> initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
> insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
> &PPCVSXFMAMutateID);
> - return false;
> }
>
> -bool PPCPassConfig::addPreSched2() {
> - addPass(createPPCVSXCopyCleanupPass());
> +void PPCPassConfig::addPreSched2() {
> + addPass(createPPCVSXCopyCleanupPass(), false);
>
> if (getOptLevel() != CodeGenOpt::None)
> addPass(&IfConverterID);
> -
> - return true;
> }
>
> -bool PPCPassConfig::addPreEmitPass() {
> +void PPCPassConfig::addPreEmitPass() {
> if (getOptLevel() != CodeGenOpt::None)
> - addPass(createPPCEarlyReturnPass());
> + addPass(createPPCEarlyReturnPass(), false);
> // Must run branch selection immediately preceding the asm printer.
> - addPass(createPPCBranchSelectionPass());
> - return false;
> + addPass(createPPCBranchSelectionPass(), false);
> }
>
> void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
>
> Modified: llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp?rev=224042&r1=224041&r2=224042&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp Thu Dec 11 13:42:05 2014
> @@ -87,10 +87,10 @@ public:
> void addCodeGenPrepare() override;
> bool addPreISel() override;
> bool addInstSelector() override;
> - bool addPreRegAlloc() override;
> - bool addPostRegAlloc() override;
> - bool addPreSched2() override;
> - bool addPreEmitPass() override;
> + void addPreRegAlloc() override;
> + void addPostRegAlloc() override;
> + void addPreSched2() override;
> + void addPreEmitPass() override;
> };
> } // End of anonymous namespace
>
> @@ -163,7 +163,7 @@ bool AMDGPUPassConfig::addInstSelector()
> return false;
> }
>
> -bool AMDGPUPassConfig::addPreRegAlloc() {
> +void AMDGPUPassConfig::addPreRegAlloc() {
> const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
>
> if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
> @@ -179,47 +179,42 @@ bool AMDGPUPassConfig::addPreRegAlloc()
> insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
> }
>
> - addPass(createSIShrinkInstructionsPass());
> - addPass(createSIFixSGPRLiveRangesPass());
> + addPass(createSIShrinkInstructionsPass(), false);
> + addPass(createSIFixSGPRLiveRangesPass(), false);
> }
> - return false;
> }
>
> -bool AMDGPUPassConfig::addPostRegAlloc() {
> +void AMDGPUPassConfig::addPostRegAlloc() {
> const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
>
> if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
> - addPass(createSIShrinkInstructionsPass());
> + addPass(createSIShrinkInstructionsPass(), false);
> }
> - return false;
> }
>
> -bool AMDGPUPassConfig::addPreSched2() {
> +void AMDGPUPassConfig::addPreSched2() {
> const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
>
> if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
> - addPass(createR600EmitClauseMarkers());
> + addPass(createR600EmitClauseMarkers(), false);
> if (ST.isIfCvtEnabled())
> - addPass(&IfConverterID);
> + addPass(&IfConverterID, false);
> if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
> - addPass(createR600ClauseMergePass(*TM));
> + addPass(createR600ClauseMergePass(*TM), false);
> if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
> - addPass(createSIInsertWaits(*TM));
> + addPass(createSIInsertWaits(*TM), false);
> }
> - return false;
> }
>
> -bool AMDGPUPassConfig::addPreEmitPass() {
> +void AMDGPUPassConfig::addPreEmitPass() {
> const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
> if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
> - addPass(createAMDGPUCFGStructurizerPass());
> - addPass(createR600ExpandSpecialInstrsPass(*TM));
> - addPass(&FinalizeMachineBundlesID);
> - addPass(createR600Packetizer(*TM));
> - addPass(createR600ControlFlowFinalizer(*TM));
> + addPass(createAMDGPUCFGStructurizerPass(), false);
> + addPass(createR600ExpandSpecialInstrsPass(*TM), false);
> + addPass(&FinalizeMachineBundlesID, false);
> + addPass(createR600Packetizer(*TM), false);
> + addPass(createR600ControlFlowFinalizer(*TM), false);
> } else {
> - addPass(createSILowerControlFlowPass(*TM));
> + addPass(createSILowerControlFlowPass(*TM), false);
> }
> -
> - return false;
> }
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=224042&r1=224041&r2=224042&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Thu Dec 11 13:42:05 2014
> @@ -53,7 +53,7 @@ public:
>
> void addIRPasses() override;
> bool addInstSelector() override;
> - bool addPreEmitPass() override;
> + void addPreEmitPass() override;
> };
> } // namespace
>
> @@ -72,12 +72,8 @@ bool SparcPassConfig::addInstSelector()
> return false;
> }
>
> -/// addPreEmitPass - This pass may be implemented by targets that want to run
> -/// passes immediately before machine code is emitted. This should return
> -/// true if -print-machineinstrs should print out the code after the passes.
> -bool SparcPassConfig::addPreEmitPass(){
> +void SparcPassConfig::addPreEmitPass(){
> addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
> - return true;
> }
>
> void SparcV8TargetMachine::anchor() { }
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=224042&r1=224041&r2=224042&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp Thu Dec 11 13:42:05 2014
> @@ -46,8 +46,8 @@ public:
>
> void addIRPasses() override;
> bool addInstSelector() override;
> - bool addPreSched2() override;
> - bool addPreEmitPass() override;
> + void addPreSched2() override;
> + void addPreEmitPass() override;
> };
> } // end anonymous namespace
>
> @@ -60,14 +60,13 @@ bool SystemZPassConfig::addInstSelector(
> return false;
> }
>
> -bool SystemZPassConfig::addPreSched2() {
> +void SystemZPassConfig::addPreSched2() {
> if (getOptLevel() != CodeGenOpt::None &&
> getSystemZTargetMachine().getSubtargetImpl()->hasLoadStoreOnCond())
> addPass(&IfConverterID);
> - return true;
> }
>
> -bool SystemZPassConfig::addPreEmitPass() {
> +void SystemZPassConfig::addPreEmitPass() {
> // We eliminate comparisons here rather than earlier because some
> // transformations can change the set of available CC values and we
> // generally want those transformations to have priority. This is
> @@ -92,11 +91,10 @@ bool SystemZPassConfig::addPreEmitPass()
> // between the comparison and the branch, but it isn't clear whether
> // preventing that would be a win or not.
> if (getOptLevel() != CodeGenOpt::None)
> - addPass(createSystemZElimComparePass(getSystemZTargetMachine()));
> + addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false);
> if (getOptLevel() != CodeGenOpt::None)
> - addPass(createSystemZShortenInstPass(getSystemZTargetMachine()));
> + addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false);
> addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
> - return true;
> }
>
> TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {
>
> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=224042&r1=224041&r2=224042&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Dec 11 13:42:05 2014
> @@ -154,9 +154,8 @@ public:
> void addIRPasses() override;
> bool addInstSelector() override;
> bool addILPOpts() override;
> - bool addPreRegAlloc() override;
> - bool addPostRegAlloc() override;
> - bool addPreEmitPass() override;
> + void addPostRegAlloc() override;
> + void addPreEmitPass() override;
> };
> } // namespace
>
> @@ -188,32 +187,19 @@ bool X86PassConfig::addILPOpts() {
> return true;
> }
>
> -bool X86PassConfig::addPreRegAlloc() {
> - return false; // -print-machineinstr shouldn't print after this.
> -}
> -
> -bool X86PassConfig::addPostRegAlloc() {
> +void X86PassConfig::addPostRegAlloc() {
> addPass(createX86FloatingPointStackifierPass());
> - return true; // -print-machineinstr should print after this.
> }
>
> -bool X86PassConfig::addPreEmitPass() {
> - bool ShouldPrint = false;
> - if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
> - addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
> - ShouldPrint = true;
> - }
> +void X86PassConfig::addPreEmitPass() {
> + if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2())
> + addPass(createExecutionDependencyFixPass(&X86::VR128RegClass), false);
>
> - if (UseVZeroUpper) {
> - addPass(createX86IssueVZeroUpperPass());
> - ShouldPrint = true;
> - }
> + if (UseVZeroUpper)
> + addPass(createX86IssueVZeroUpperPass(), false);
>
> if (getOptLevel() != CodeGenOpt::None) {
> - addPass(createX86PadShortFunctions());
> + addPass(createX86PadShortFunctions(), false);
> addPass(createX86FixupLEAs());
> - ShouldPrint = true;
> }
> -
> - return ShouldPrint;
> }
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=224042&r1=224041&r2=224042&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Thu Dec 11 13:42:05 2014
> @@ -48,7 +48,7 @@ public:
> void addIRPasses() override;
> bool addPreISel() override;
> bool addInstSelector() override;
> - bool addPreEmitPass() override;
> + void addPreEmitPass() override;
> };
> } // namespace
>
> @@ -72,9 +72,8 @@ bool XCorePassConfig::addInstSelector()
> return false;
> }
>
> -bool XCorePassConfig::addPreEmitPass() {
> - addPass(createXCoreFrameToArgsOffsetEliminationPass());
> - return false;
> +void XCorePassConfig::addPreEmitPass() {
> + addPass(createXCoreFrameToArgsOffsetEliminationPass(), false);
> }
>
> // Force static initialization.
>
>
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