[llvm] r224045 - This reverts commit r224043 and r224042.
Rafael Espindola
rafael.espindola at gmail.com
Thu Dec 11 12:03:58 PST 2014
Author: rafael
Date: Thu Dec 11 14:03:57 2014
New Revision: 224045
URL: http://llvm.org/viewvc/llvm-project?rev=224045&view=rev
Log:
This reverts commit r224043 and r224042.
check-llvm was failing.
Modified:
llvm/trunk/include/llvm/CodeGen/Passes.h
llvm/trunk/lib/CodeGen/Passes.cpp
llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp
llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp
llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp
llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp
llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
Modified: llvm/trunk/include/llvm/CodeGen/Passes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=224045&r1=224044&r2=224045&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/Passes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/Passes.h Thu Dec 11 14:03:57 2014
@@ -105,7 +105,6 @@ private:
AnalysisID StopAfter;
bool Started;
bool Stopped;
- bool AddingMachinePasses;
protected:
TargetMachine *TM;
@@ -260,9 +259,12 @@ protected:
return false;
}
- /// This method may be implemented by targets that want to run passes
- /// immediately before register allocation.
- virtual void addPreRegAlloc() { }
+ /// addPreRegAlloc - This method may be implemented by targets that want to
+ /// run passes immediately before register allocation. This should return
+ /// true if -print-machineinstrs should print after these passes.
+ virtual bool addPreRegAlloc() {
+ return false;
+ }
/// createTargetRegisterAllocator - Create the register allocator pass for
/// this target at the current optimization level.
@@ -288,16 +290,24 @@ protected:
return false;
}
- /// This method may be implemented by targets that want to run passes after
- /// register allocation pass pipeline but before prolog-epilog insertion.
- virtual void addPostRegAlloc() { }
+ /// addPostRegAlloc - This method may be implemented by targets that want to
+ /// run passes after register allocation pass pipeline but before
+ /// prolog-epilog insertion. This should return true if -print-machineinstrs
+ /// should print after these passes.
+ virtual bool addPostRegAlloc() {
+ return false;
+ }
/// Add passes that optimize machine instructions after register allocation.
virtual void addMachineLateOptimization();
- /// This method may be implemented by targets that want to run passes after
- /// prolog-epilog insertion and before the second instruction scheduling pass.
- virtual void addPreSched2() { }
+ /// addPreSched2 - This method may be implemented by targets that want to
+ /// run passes after prolog-epilog insertion and before the second instruction
+ /// scheduling pass. This should return true if -print-machineinstrs should
+ /// print after these passes.
+ virtual bool addPreSched2() {
+ return false;
+ }
/// addGCPasses - Add late codegen passes that analyze code for garbage
/// collection. This should return true if GC info should be printed after
@@ -307,30 +317,24 @@ protected:
/// Add standard basic block placement passes.
virtual void addBlockPlacement();
- /// This pass may be implemented by targets that want to run passes
- /// immediately before machine code is emitted.
- virtual void addPreEmitPass() { }
+ /// addPreEmitPass - This pass may be implemented by targets that want to run
+ /// passes immediately before machine code is emitted. This should return
+ /// true if -print-machineinstrs should print out the code after the passes.
+ virtual bool addPreEmitPass() {
+ return false;
+ }
/// Utilities for targets to add passes to the pass manager.
///
/// Add a CodeGen pass at this point in the pipeline after checking overrides.
/// Return the pass that was added, or zero if no pass was added.
- /// @p printAfter if true and adding a machine function pass add an extra
- /// machine printer pass afterwards
- /// @p verifyAfter if true and adding a machine function pass add an extra
- /// machine verification pass afterwards.
- AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
- bool printAfter = true);
+ AnalysisID addPass(AnalysisID PassID);
/// Add a pass to the PassManager if that pass is supposed to be run, as
/// determined by the StartAfter and StopAfter options. Takes ownership of the
/// pass.
- /// @p printAfter if true and adding a machine function pass add an extra
- /// machine printer pass afterwards
- /// @p verifyAfter if true and adding a machine function pass add an extra
- /// machine verification pass afterwards.
- void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
+ void addPass(Pass *P);
/// addMachinePasses helper to create the target-selected or overriden
/// regalloc pass.
@@ -339,14 +343,7 @@ protected:
/// printAndVerify - Add a pass to dump then verify the machine function, if
/// those steps are enabled.
///
- void printAndVerify(const std::string &Banner);
-
- /// Add a pass to print the machine function if printing is enabled.
- void addPrintPass(const std::string &Banner);
-
- /// Add a pass to perform basic verification of the machine function if
- /// verification is enabled.
- void addVerifyPass(const std::string &Banner);
+ void printAndVerify(const char *Banner);
};
} // namespace llvm
Modified: llvm/trunk/lib/CodeGen/Passes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Passes.cpp?rev=224045&r1=224044&r2=224045&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Passes.cpp (original)
+++ llvm/trunk/lib/CodeGen/Passes.cpp Thu Dec 11 14:03:57 2014
@@ -235,8 +235,8 @@ TargetPassConfig::~TargetPassConfig() {
// registers all common codegen passes.
TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
: ImmutablePass(ID), PM(&pm), StartAfter(nullptr), StopAfter(nullptr),
- Started(true), Stopped(false), AddingMachinePasses(false), TM(tm),
- Impl(nullptr), Initialized(false), DisableVerify(false),
+ Started(true), Stopped(false), TM(tm), Impl(nullptr), Initialized(false),
+ DisableVerify(false),
EnableTailMerge(true) {
Impl = new PassConfigImpl();
@@ -304,7 +304,7 @@ IdentifyingPassPtr TargetPassConfig::get
/// a later pass or that it should stop after an earlier pass, then do not add
/// the pass. Finally, compare the current pass against the StartAfter
/// and StopAfter options and change the Started/Stopped flags accordingly.
-void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
+void TargetPassConfig::addPass(Pass *P) {
assert(!Initialized && "PassConfig is immutable");
// Cache the Pass ID here in case the pass manager finds this pass is
@@ -313,18 +313,10 @@ void TargetPassConfig::addPass(Pass *P,
// and shouldn't reference it.
AnalysisID PassID = P->getPassID();
- if (Started && !Stopped) {
+ if (Started && !Stopped)
PM->add(P);
- if (AddingMachinePasses) {
- std::string Banner = std::string("After ")+std::string(P->getPassName());
- if (printAfter)
- addPrintPass(Banner);
- if (verifyAfter)
- addVerifyPass(Banner);
- }
- } else {
+ else
delete P;
- }
if (StopAfter == PassID)
Stopped = true;
if (StartAfter == PassID)
@@ -338,8 +330,7 @@ void TargetPassConfig::addPass(Pass *P,
///
/// addPass cannot return a pointer to the pass instance because is internal the
/// PassManager and the instance we create here may already be freed.
-AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
- bool printAfter) {
+AnalysisID TargetPassConfig::addPass(AnalysisID PassID) {
IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
if (!FinalPtr.isValid())
@@ -354,7 +345,7 @@ AnalysisID TargetPassConfig::addPass(Ana
llvm_unreachable("Pass ID not registered");
}
AnalysisID FinalID = P->getPassID();
- addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
+ addPass(P); // Ends the lifetime of P.
// Add the passes after the pass P if there is any.
for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator
@@ -369,25 +360,18 @@ AnalysisID TargetPassConfig::addPass(Ana
NP = Pass::createPass((*I).second.getID());
assert(NP && "Pass ID not registered");
}
- addPass(NP, false, false);
+ addPass(NP);
}
}
return FinalID;
}
-void TargetPassConfig::printAndVerify(const std::string &Banner) {
- addPrintPass(Banner);
- addVerifyPass(Banner);
-}
-
-void TargetPassConfig::addPrintPass(const std::string &Banner) {
+void TargetPassConfig::printAndVerify(const char *Banner) {
if (TM->shouldPrintMachineCode())
- PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
-}
+ addPass(createMachineFunctionPrinterPass(dbgs(), Banner));
-void TargetPassConfig::addVerifyPass(const std::string &Banner) {
if (VerifyMachineCode)
- PM->add(createMachineVerifierPass(Banner));
+ addPass(createMachineVerifierPass(Banner));
}
/// Add common target configurable passes that perform LLVM IR to IR transforms
@@ -507,8 +491,6 @@ void TargetPassConfig::addISelPrepare()
/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
/// before/after any target-independent pass. But it's currently overkill.
void TargetPassConfig::addMachinePasses() {
- AddingMachinePasses = true;
-
// Insert a machine instr printer pass after the specified pass.
// If -print-machineinstrs specified, print machineinstrs after all passes.
if (StringRef(PrintMachineInstrs.getValue()).equals(""))
@@ -528,7 +510,8 @@ void TargetPassConfig::addMachinePasses(
printAndVerify("After Instruction Selection");
// Expand pseudo-instructions emitted by ISel.
- addPass(&ExpandISelPseudosID);
+ if (addPass(&ExpandISelPseudosID))
+ printAndVerify("After ExpandISelPseudos");
// Add passes that optimize machine instructions in SSA form.
if (getOptLevel() != CodeGenOpt::None) {
@@ -536,11 +519,12 @@ void TargetPassConfig::addMachinePasses(
} else {
// If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible.
- addPass(&LocalStackSlotAllocationID, false);
+ addPass(&LocalStackSlotAllocationID);
}
// Run pre-ra passes.
- addPreRegAlloc();
+ if (addPreRegAlloc())
+ printAndVerify("After PreRegAlloc passes");
// Run register allocation and passes that are tightly coupled with it,
// including phi elimination and scheduling.
@@ -550,10 +534,12 @@ void TargetPassConfig::addMachinePasses(
addFastRegAlloc(createRegAllocPass(false));
// Run post-ra passes.
- addPostRegAlloc();
+ if (addPostRegAlloc())
+ printAndVerify("After PostRegAlloc passes");
// Insert prolog/epilog code. Eliminate abstract frame index references...
addPass(&PrologEpilogCodeInserterID);
+ printAndVerify("After PrologEpilogCodeInserter");
/// Add passes that optimize machine instructions after register allocation.
if (getOptLevel() != CodeGenOpt::None)
@@ -561,9 +547,11 @@ void TargetPassConfig::addMachinePasses(
// Expand pseudo instructions before second scheduling pass.
addPass(&ExpandPostRAPseudosID);
+ printAndVerify("After ExpandPostRAPseudos");
// Run pre-sched2 passes.
- addPreSched2();
+ if (addPreSched2())
+ printAndVerify("After PreSched2 passes");
// Second pass scheduler.
if (getOptLevel() != CodeGenOpt::None) {
@@ -571,61 +559,66 @@ void TargetPassConfig::addMachinePasses(
addPass(&PostMachineSchedulerID);
else
addPass(&PostRASchedulerID);
+ printAndVerify("After PostRAScheduler");
}
// GC
if (addGCPasses()) {
if (PrintGCInfo)
- addPass(createGCInfoPrinter(dbgs()), false, false);
+ addPass(createGCInfoPrinter(dbgs()));
}
// Basic block placement.
if (getOptLevel() != CodeGenOpt::None)
addBlockPlacement();
- addPreEmitPass();
-
- addPass(&StackMapLivenessID, false);
+ if (addPreEmitPass())
+ printAndVerify("After PreEmit passes");
- AddingMachinePasses = false;
+ addPass(&StackMapLivenessID);
}
/// Add passes that optimize machine instructions in SSA form.
void TargetPassConfig::addMachineSSAOptimization() {
// Pre-ra tail duplication.
- addPass(&EarlyTailDuplicateID);
+ if (addPass(&EarlyTailDuplicateID))
+ printAndVerify("After Pre-RegAlloc TailDuplicate");
// Optimize PHIs before DCE: removing dead PHI cycles may make more
// instructions dead.
- addPass(&OptimizePHIsID, false);
+ addPass(&OptimizePHIsID);
// This pass merges large allocas. StackSlotColoring is a different pass
// which merges spill slots.
- addPass(&StackColoringID, false);
+ addPass(&StackColoringID);
// If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible.
- addPass(&LocalStackSlotAllocationID, false);
+ addPass(&LocalStackSlotAllocationID);
// With optimization, dead code should already be eliminated. However
// there is one known exception: lowered code for arguments that are only
// used by tail calls, where the tail calls reuse the incoming stack
// arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
addPass(&DeadMachineInstructionElimID);
+ printAndVerify("After codegen DCE pass");
// Allow targets to insert passes that improve instruction level parallelism,
// like if-conversion. Such passes will typically need dominator trees and
// loop info, just like LICM and CSE below.
- addILPOpts();
+ if (addILPOpts())
+ printAndVerify("After ILP optimizations");
- addPass(&MachineLICMID, false);
- addPass(&MachineCSEID, false);
+ addPass(&MachineLICMID);
+ addPass(&MachineCSEID);
addPass(&MachineSinkingID);
+ printAndVerify("After Machine LICM, CSE and Sinking passes");
- addPass(&PeepholeOptimizerID, false);
+ addPass(&PeepholeOptimizerID);
// Clean-up the dead code that may have been generated by peephole
// rewriting.
addPass(&DeadMachineInstructionElimID);
+ printAndVerify("After codegen peephole optimization pass");
}
//===---------------------------------------------------------------------===//
@@ -708,17 +701,18 @@ bool TargetPassConfig::usingDefaultRegAl
/// Add the minimum set of target-independent passes that are required for
/// register allocation. No coalescing or scheduling.
void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
- addPass(&PHIEliminationID, false);
- addPass(&TwoAddressInstructionPassID, false);
+ addPass(&PHIEliminationID);
+ addPass(&TwoAddressInstructionPassID);
addPass(RegAllocPass);
+ printAndVerify("After Register Allocation");
}
/// Add standard target-independent passes that are tightly coupled with
/// optimized register allocation, including coalescing, machine instruction
/// scheduling, and register allocation itself.
void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
- addPass(&ProcessImplicitDefsID, false);
+ addPass(&ProcessImplicitDefsID);
// LiveVariables currently requires pure SSA form.
//
@@ -726,30 +720,35 @@ void TargetPassConfig::addOptimizedRegAl
// LiveVariables can be removed completely, and LiveIntervals can be directly
// computed. (We still either need to regenerate kill flags after regalloc, or
// preferably fix the scavenger to not depend on them).
- addPass(&LiveVariablesID, false);
+ addPass(&LiveVariablesID);
// Edge splitting is smarter with machine loop info.
- addPass(&MachineLoopInfoID, false);
- addPass(&PHIEliminationID, false);
+ addPass(&MachineLoopInfoID);
+ addPass(&PHIEliminationID);
// Eventually, we want to run LiveIntervals before PHI elimination.
if (EarlyLiveIntervals)
- addPass(&LiveIntervalsID, false);
+ addPass(&LiveIntervalsID);
- addPass(&TwoAddressInstructionPassID, false);
+ addPass(&TwoAddressInstructionPassID);
addPass(&RegisterCoalescerID);
+ printAndVerify("After Register Coalescing");
// PreRA instruction scheduling.
- addPass(&MachineSchedulerID);
+ if (addPass(&MachineSchedulerID))
+ printAndVerify("After Machine Scheduling");
// Add the selected register allocation pass.
addPass(RegAllocPass);
+ printAndVerify("After Register Allocation, before rewriter");
// Allow targets to change the register assignments before rewriting.
- addPreRewrite();
+ if (addPreRewrite())
+ printAndVerify("After pre-rewrite passes");
// Finally rewrite virtual registers.
addPass(&VirtRegRewriterID);
+ printAndVerify("After Virtual Register Rewriter");
// Perform stack slot coloring and post-ra machine LICM.
//
@@ -761,6 +760,8 @@ void TargetPassConfig::addOptimizedRegAl
//
// FIXME: can this move into MachineLateOptimization?
addPass(&PostRAMachineLICMID);
+
+ printAndVerify("After StackSlotColoring and postra Machine LICM");
}
//===---------------------------------------------------------------------===//
@@ -770,30 +771,34 @@ void TargetPassConfig::addOptimizedRegAl
/// Add passes that optimize machine instructions after register allocation.
void TargetPassConfig::addMachineLateOptimization() {
// Branch folding must be run after regalloc and prolog/epilog insertion.
- addPass(&BranchFolderPassID);
+ if (addPass(&BranchFolderPassID))
+ printAndVerify("After BranchFolding");
// Tail duplication.
// Note that duplicating tail just increases code size and degrades
// performance for targets that require Structured Control Flow.
// In addition it can also make CFG irreducible. Thus we disable it.
- if (!TM->requiresStructuredCFG())
- addPass(&TailDuplicateID);
+ if (!TM->requiresStructuredCFG() && addPass(&TailDuplicateID))
+ printAndVerify("After TailDuplicate");
// Copy propagation.
- addPass(&MachineCopyPropagationID);
+ if (addPass(&MachineCopyPropagationID))
+ printAndVerify("After copy propagation pass");
}
/// Add standard GC passes.
bool TargetPassConfig::addGCPasses() {
- addPass(&GCMachineCodeAnalysisID, false);
+ addPass(&GCMachineCodeAnalysisID);
return true;
}
/// Add standard basic block placement passes.
void TargetPassConfig::addBlockPlacement() {
- if (addPass(&MachineBlockPlacementID, false)) {
+ if (addPass(&MachineBlockPlacementID)) {
// Run a separate pass to collect block placement statistics.
if (EnableBlockPlacementStats)
addPass(&MachineBlockPlacementStatsID);
+
+ printAndVerify("After machine block placement.");
}
}
Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=224045&r1=224044&r2=224045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp Thu Dec 11 14:03:57 2014
@@ -181,10 +181,10 @@ public:
bool addPreISel() override;
bool addInstSelector() override;
bool addILPOpts() override;
- void addPreRegAlloc() override;
- void addPostRegAlloc() override;
- void addPreSched2() override;
- void addPreEmitPass() override;
+ bool addPreRegAlloc() override;
+ bool addPostRegAlloc() override;
+ bool addPreSched2() override;
+ bool addPreEmitPass() override;
};
} // namespace
@@ -267,7 +267,7 @@ bool AArch64PassConfig::addILPOpts() {
return true;
}
-void AArch64PassConfig::addPreRegAlloc() {
+bool AArch64PassConfig::addPreRegAlloc() {
// Use AdvSIMD scalar instructions whenever profitable.
if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
addPass(createAArch64AdvSIMDScalar());
@@ -275,9 +275,10 @@ void AArch64PassConfig::addPreRegAlloc()
// be register coaleascer friendly.
addPass(&PeepholeOptimizerID);
}
+ return true;
}
-void AArch64PassConfig::addPostRegAlloc() {
+bool AArch64PassConfig::addPostRegAlloc() {
// Change dead register definitions to refer to the zero register.
if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
addPass(createAArch64DeadRegisterDefinitions());
@@ -287,17 +288,19 @@ void AArch64PassConfig::addPostRegAlloc(
usingDefaultRegAlloc())
// Improve performance for some FP/SIMD code for A57.
addPass(createAArch64A57FPLoadBalancing());
+ return true;
}
-void AArch64PassConfig::addPreSched2() {
+bool AArch64PassConfig::addPreSched2() {
// Expand some pseudo instructions to allow proper scheduling.
addPass(createAArch64ExpandPseudoPass());
// Use load/store pair instructions when possible.
if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
addPass(createAArch64LoadStoreOptimizationPass());
+ return true;
}
-void AArch64PassConfig::addPreEmitPass() {
+bool AArch64PassConfig::addPreEmitPass() {
if (EnableA53Fix835769)
addPass(createAArch64A53Fix835769());
// Relax conditional branch instructions if they're otherwise out of
@@ -306,4 +309,5 @@ void AArch64PassConfig::addPreEmitPass()
if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
addPass(createAArch64CollectLOHPass());
+ return true;
}
Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=224045&r1=224044&r2=224045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Dec 11 14:03:57 2014
@@ -197,9 +197,9 @@ public:
void addIRPasses() override;
bool addPreISel() override;
bool addInstSelector() override;
- void addPreRegAlloc() override;
- void addPreSched2() override;
- void addPreEmitPass() override;
+ bool addPreRegAlloc() override;
+ bool addPreSched2() override;
+ bool addPreEmitPass() override;
};
} // namespace
@@ -241,7 +241,7 @@ bool ARMPassConfig::addInstSelector() {
return false;
}
-void ARMPassConfig::addPreRegAlloc() {
+bool ARMPassConfig::addPreRegAlloc() {
if (getOptLevel() != CodeGenOpt::None)
addPass(createARMLoadStoreOptimizationPass(true));
if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
@@ -252,11 +252,13 @@ void ARMPassConfig::addPreRegAlloc() {
getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
addPass(createA15SDOptimizerPass());
}
+ return true;
}
-void ARMPassConfig::addPreSched2() {
+bool ARMPassConfig::addPreSched2() {
if (getOptLevel() != CodeGenOpt::None) {
addPass(createARMLoadStoreOptimizationPass());
+ printAndVerify("After ARM load / store optimizer");
if (getARMSubtarget().hasNEON())
addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
@@ -277,9 +279,11 @@ void ARMPassConfig::addPreSched2() {
}
if (getARMSubtarget().isThumb2())
addPass(createThumb2ITBlockPass());
+
+ return true;
}
-void ARMPassConfig::addPreEmitPass() {
+bool ARMPassConfig::addPreEmitPass() {
if (getARMSubtarget().isThumb2()) {
if (!getARMSubtarget().prefers32BitThumb())
addPass(createThumb2SizeReductionPass());
@@ -290,4 +294,6 @@ void ARMPassConfig::addPreEmitPass() {
addPass(createARMOptimizeBarriersPass());
addPass(createARMConstantIslandPass());
+
+ return true;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp?rev=224045&r1=224044&r2=224045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp Thu Dec 11 14:03:57 2014
@@ -103,10 +103,10 @@ public:
}
bool addInstSelector() override;
- void addPreRegAlloc() override;
- void addPostRegAlloc() override;
- void addPreSched2() override;
- void addPreEmitPass() override;
+ bool addPreRegAlloc() override;
+ bool addPostRegAlloc() override;
+ bool addPreSched2() override;
+ bool addPreEmitPass() override;
};
} // namespace
@@ -131,45 +131,51 @@ bool HexagonPassConfig::addInstSelector(
return false;
}
-void HexagonPassConfig::addPreRegAlloc() {
+bool HexagonPassConfig::addPreRegAlloc() {
if (getOptLevel() != CodeGenOpt::None)
if (!DisableHardwareLoops)
- addPass(createHexagonHardwareLoops(), false);
+ addPass(createHexagonHardwareLoops());
+ return false;
}
-void HexagonPassConfig::addPostRegAlloc() {
+bool HexagonPassConfig::addPostRegAlloc() {
const HexagonTargetMachine &TM = getHexagonTargetMachine();
if (getOptLevel() != CodeGenOpt::None)
if (!DisableHexagonCFGOpt)
- addPass(createHexagonCFGOptimizer(TM), false);
+ addPass(createHexagonCFGOptimizer(TM));
+ return false;
}
-void HexagonPassConfig::addPreSched2() {
+bool HexagonPassConfig::addPreSched2() {
const HexagonTargetMachine &TM = getHexagonTargetMachine();
- addPass(createHexagonCopyToCombine(), false);
+ addPass(createHexagonCopyToCombine());
if (getOptLevel() != CodeGenOpt::None)
- addPass(&IfConverterID, false);
+ addPass(&IfConverterID);
addPass(createHexagonSplitConst32AndConst64(TM));
+ printAndVerify("After hexagon split const32/64 pass");
+ return true;
}
-void HexagonPassConfig::addPreEmitPass() {
+bool HexagonPassConfig::addPreEmitPass() {
const HexagonTargetMachine &TM = getHexagonTargetMachine();
bool NoOpt = (getOptLevel() == CodeGenOpt::None);
if (!NoOpt)
- addPass(createHexagonNewValueJump(), false);
+ addPass(createHexagonNewValueJump());
// Expand Spill code for predicate registers.
- addPass(createHexagonExpandPredSpillCode(TM), false);
+ addPass(createHexagonExpandPredSpillCode(TM));
// Split up TFRcondsets into conditional transfers.
- addPass(createHexagonSplitTFRCondSets(TM), false);
+ addPass(createHexagonSplitTFRCondSets(TM));
// Create Packets.
if (!NoOpt) {
if (!DisableHardwareLoops)
- addPass(createHexagonFixupHwLoops(), false);
- addPass(createHexagonPacketizer(), false);
+ addPass(createHexagonFixupHwLoops());
+ addPass(createHexagonPacketizer());
}
+
+ return false;
}
Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=224045&r1=224044&r2=224045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Thu Dec 11 14:03:57 2014
@@ -50,7 +50,7 @@ public:
}
bool addInstSelector() override;
- void addPreEmitPass() override;
+ bool addPreEmitPass() override;
};
} // namespace
@@ -64,7 +64,8 @@ bool MSP430PassConfig::addInstSelector()
return false;
}
-void MSP430PassConfig::addPreEmitPass() {
+bool MSP430PassConfig::addPreEmitPass() {
// Must run branch selection immediately preceding the asm printer.
- addPass(createMSP430BranchSelectionPass(), false);
+ addPass(createMSP430BranchSelectionPass());
+ return false;
}
Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=224045&r1=224044&r2=224045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Thu Dec 11 14:03:57 2014
@@ -170,9 +170,9 @@ public:
void addIRPasses() override;
bool addInstSelector() override;
void addMachineSSAOptimization() override;
- void addPreEmitPass() override;
+ bool addPreEmitPass() override;
- void addPreRegAlloc() override;
+ bool addPreRegAlloc() override;
};
} // namespace
@@ -203,9 +203,13 @@ void MipsPassConfig::addMachineSSAOptimi
TargetPassConfig::addMachineSSAOptimization();
}
-void MipsPassConfig::addPreRegAlloc() {
- if (getOptLevel() == CodeGenOpt::None)
+bool MipsPassConfig::addPreRegAlloc() {
+ if (getOptLevel() == CodeGenOpt::None) {
addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
+ return true;
+ }
+ else
+ return false;
}
void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
@@ -224,9 +228,10 @@ void MipsTargetMachine::addAnalysisPasse
// Implemented by targets that want to run passes immediately before
// machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes.
-void MipsPassConfig::addPreEmitPass() {
+bool MipsPassConfig::addPreEmitPass() {
MipsTargetMachine &TM = getMipsTargetMachine();
addPass(createMipsDelaySlotFillerPass(TM));
addPass(createMipsLongBranchPass(TM));
addPass(createMipsConstantIslandPass(TM));
+ return true;
}
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp?rev=224045&r1=224044&r2=224045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp Thu Dec 11 14:03:57 2014
@@ -110,7 +110,8 @@ public:
void addIRPasses() override;
bool addInstSelector() override;
- void addPostRegAlloc() override;
+ bool addPreRegAlloc() override;
+ bool addPostRegAlloc() override;
void addMachineSSAOptimization() override;
FunctionPass *createTargetRegisterAllocator(bool) override;
@@ -182,8 +183,10 @@ bool NVPTXPassConfig::addInstSelector()
return false;
}
-void NVPTXPassConfig::addPostRegAlloc() {
- addPass(createNVPTXPrologEpilogPass(), false);
+bool NVPTXPassConfig::addPreRegAlloc() { return false; }
+bool NVPTXPassConfig::addPostRegAlloc() {
+ addPass(createNVPTXPrologEpilogPass());
+ return false;
}
FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=224045&r1=224044&r2=224045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Thu Dec 11 14:03:57 2014
@@ -162,9 +162,9 @@ public:
bool addPreISel() override;
bool addILPOpts() override;
bool addInstSelector() override;
- void addPreRegAlloc() override;
- void addPreSched2() override;
- void addPreEmitPass() override;
+ bool addPreRegAlloc() override;
+ bool addPreSched2() override;
+ bool addPreEmitPass() override;
};
} // namespace
@@ -216,24 +216,28 @@ bool PPCPassConfig::addInstSelector() {
return false;
}
-void PPCPassConfig::addPreRegAlloc() {
+bool PPCPassConfig::addPreRegAlloc() {
initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
&PPCVSXFMAMutateID);
+ return false;
}
-void PPCPassConfig::addPreSched2() {
- addPass(createPPCVSXCopyCleanupPass(), false);
+bool PPCPassConfig::addPreSched2() {
+ addPass(createPPCVSXCopyCleanupPass());
if (getOptLevel() != CodeGenOpt::None)
addPass(&IfConverterID);
+
+ return true;
}
-void PPCPassConfig::addPreEmitPass() {
+bool PPCPassConfig::addPreEmitPass() {
if (getOptLevel() != CodeGenOpt::None)
- addPass(createPPCEarlyReturnPass(), false);
+ addPass(createPPCEarlyReturnPass());
// Must run branch selection immediately preceding the asm printer.
- addPass(createPPCBranchSelectionPass(), false);
+ addPass(createPPCBranchSelectionPass());
+ return false;
}
void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
Modified: llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp?rev=224045&r1=224044&r2=224045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp Thu Dec 11 14:03:57 2014
@@ -87,10 +87,10 @@ public:
void addCodeGenPrepare() override;
bool addPreISel() override;
bool addInstSelector() override;
- void addPreRegAlloc() override;
- void addPostRegAlloc() override;
- void addPreSched2() override;
- void addPreEmitPass() override;
+ bool addPreRegAlloc() override;
+ bool addPostRegAlloc() override;
+ bool addPreSched2() override;
+ bool addPreEmitPass() override;
};
} // End of anonymous namespace
@@ -163,7 +163,7 @@ bool AMDGPUPassConfig::addInstSelector()
return false;
}
-void AMDGPUPassConfig::addPreRegAlloc() {
+bool AMDGPUPassConfig::addPreRegAlloc() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
@@ -179,42 +179,47 @@ void AMDGPUPassConfig::addPreRegAlloc()
insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
}
- addPass(createSIShrinkInstructionsPass(), false);
- addPass(createSIFixSGPRLiveRangesPass(), false);
+ addPass(createSIShrinkInstructionsPass());
+ addPass(createSIFixSGPRLiveRangesPass());
}
+ return false;
}
-void AMDGPUPassConfig::addPostRegAlloc() {
+bool AMDGPUPassConfig::addPostRegAlloc() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
- addPass(createSIShrinkInstructionsPass(), false);
+ addPass(createSIShrinkInstructionsPass());
}
+ return false;
}
-void AMDGPUPassConfig::addPreSched2() {
+bool AMDGPUPassConfig::addPreSched2() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
- addPass(createR600EmitClauseMarkers(), false);
+ addPass(createR600EmitClauseMarkers());
if (ST.isIfCvtEnabled())
- addPass(&IfConverterID, false);
+ addPass(&IfConverterID);
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
- addPass(createR600ClauseMergePass(*TM), false);
+ addPass(createR600ClauseMergePass(*TM));
if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
- addPass(createSIInsertWaits(*TM), false);
+ addPass(createSIInsertWaits(*TM));
}
+ return false;
}
-void AMDGPUPassConfig::addPreEmitPass() {
+bool AMDGPUPassConfig::addPreEmitPass() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
- addPass(createAMDGPUCFGStructurizerPass(), false);
- addPass(createR600ExpandSpecialInstrsPass(*TM), false);
- addPass(&FinalizeMachineBundlesID, false);
- addPass(createR600Packetizer(*TM), false);
- addPass(createR600ControlFlowFinalizer(*TM), false);
+ addPass(createAMDGPUCFGStructurizerPass());
+ addPass(createR600ExpandSpecialInstrsPass(*TM));
+ addPass(&FinalizeMachineBundlesID);
+ addPass(createR600Packetizer(*TM));
+ addPass(createR600ControlFlowFinalizer(*TM));
} else {
- addPass(createSILowerControlFlowPass(*TM), false);
+ addPass(createSILowerControlFlowPass(*TM));
}
+
+ return false;
}
Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=224045&r1=224044&r2=224045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Thu Dec 11 14:03:57 2014
@@ -53,7 +53,7 @@ public:
void addIRPasses() override;
bool addInstSelector() override;
- void addPreEmitPass() override;
+ bool addPreEmitPass() override;
};
} // namespace
@@ -72,8 +72,12 @@ bool SparcPassConfig::addInstSelector()
return false;
}
-void SparcPassConfig::addPreEmitPass(){
+/// addPreEmitPass - This pass may be implemented by targets that want to run
+/// passes immediately before machine code is emitted. This should return
+/// true if -print-machineinstrs should print out the code after the passes.
+bool SparcPassConfig::addPreEmitPass(){
addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
+ return true;
}
void SparcV8TargetMachine::anchor() { }
Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=224045&r1=224044&r2=224045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp Thu Dec 11 14:03:57 2014
@@ -46,8 +46,8 @@ public:
void addIRPasses() override;
bool addInstSelector() override;
- void addPreSched2() override;
- void addPreEmitPass() override;
+ bool addPreSched2() override;
+ bool addPreEmitPass() override;
};
} // end anonymous namespace
@@ -60,13 +60,14 @@ bool SystemZPassConfig::addInstSelector(
return false;
}
-void SystemZPassConfig::addPreSched2() {
+bool SystemZPassConfig::addPreSched2() {
if (getOptLevel() != CodeGenOpt::None &&
getSystemZTargetMachine().getSubtargetImpl()->hasLoadStoreOnCond())
addPass(&IfConverterID);
+ return true;
}
-void SystemZPassConfig::addPreEmitPass() {
+bool SystemZPassConfig::addPreEmitPass() {
// We eliminate comparisons here rather than earlier because some
// transformations can change the set of available CC values and we
// generally want those transformations to have priority. This is
@@ -91,10 +92,11 @@ void SystemZPassConfig::addPreEmitPass()
// between the comparison and the branch, but it isn't clear whether
// preventing that would be a win or not.
if (getOptLevel() != CodeGenOpt::None)
- addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false);
+ addPass(createSystemZElimComparePass(getSystemZTargetMachine()));
if (getOptLevel() != CodeGenOpt::None)
- addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false);
+ addPass(createSystemZShortenInstPass(getSystemZTargetMachine()));
addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
+ return true;
}
TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {
Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=224045&r1=224044&r2=224045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Dec 11 14:03:57 2014
@@ -154,8 +154,9 @@ public:
void addIRPasses() override;
bool addInstSelector() override;
bool addILPOpts() override;
- void addPostRegAlloc() override;
- void addPreEmitPass() override;
+ bool addPreRegAlloc() override;
+ bool addPostRegAlloc() override;
+ bool addPreEmitPass() override;
};
} // namespace
@@ -187,19 +188,32 @@ bool X86PassConfig::addILPOpts() {
return true;
}
-void X86PassConfig::addPostRegAlloc() {
+bool X86PassConfig::addPreRegAlloc() {
+ return false; // -print-machineinstr shouldn't print after this.
+}
+
+bool X86PassConfig::addPostRegAlloc() {
addPass(createX86FloatingPointStackifierPass());
+ return true; // -print-machineinstr should print after this.
}
-void X86PassConfig::addPreEmitPass() {
- if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2())
+bool X86PassConfig::addPreEmitPass() {
+ bool ShouldPrint = false;
+ if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
+ ShouldPrint = true;
+ }
- if (UseVZeroUpper)
+ if (UseVZeroUpper) {
addPass(createX86IssueVZeroUpperPass());
+ ShouldPrint = true;
+ }
if (getOptLevel() != CodeGenOpt::None) {
addPass(createX86PadShortFunctions());
addPass(createX86FixupLEAs());
+ ShouldPrint = true;
}
+
+ return ShouldPrint;
}
Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=224045&r1=224044&r2=224045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Thu Dec 11 14:03:57 2014
@@ -48,7 +48,7 @@ public:
void addIRPasses() override;
bool addPreISel() override;
bool addInstSelector() override;
- void addPreEmitPass() override;
+ bool addPreEmitPass() override;
};
} // namespace
@@ -72,8 +72,9 @@ bool XCorePassConfig::addInstSelector()
return false;
}
-void XCorePassConfig::addPreEmitPass() {
- addPass(createXCoreFrameToArgsOffsetEliminationPass(), false);
+bool XCorePassConfig::addPreEmitPass() {
+ addPass(createXCoreFrameToArgsOffsetEliminationPass());
+ return false;
}
// Force static initialization.
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