[llvm] r224027 - [Hexagon] Ading i64 <- i32, i32 sextw pattern.

[Colin LeMahieu]

Author: colinl
Date: Thu Dec 11 11:08:21 2014
New Revision: 224027

URL: http://llvm.org/viewvc/llvm-project?rev=224027&view=rev
Log:
[Hexagon] Ading i64 <- i32, i32 sextw pattern.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=224027&r1=224026&r2=224027&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Thu Dec 11 11:08:21 2014
@@ -2226,6 +2226,8 @@ class T_S2op_1_di <string mnemonic, bits
 let isCodeGenOnly = 0 in
 def A2_sxtw   : T_S2op_1_di <"sxtw", 0b01, 0b000>;
 
+def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>;
+
 //===----------------------------------------------------------------------===//
 // STYPE/ALU -
 //===----------------------------------------------------------------------===//