[llvm] r223933 - [Hexagon] Adding JR class predicated call reg instructions.

[Colin LeMahieu]

Author: colinl
Date: Wed Dec 10 12:24:16 2014
New Revision: 223933

URL: http://llvm.org/viewvc/llvm-project?rev=223933&view=rev
Log:
[Hexagon] Adding JR class predicated call reg instructions.

Added:
    llvm/trunk/test/MC/Disassembler/Hexagon/jr.txt
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
    llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=223933&r1=223932&r2=223933&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Wed Dec 10 12:24:16 2014
@@ -1383,6 +1383,34 @@ multiclass JMPR_base<string BaseOp> {
   }
 }
 
+let isCall = 1, hasSideEffects = 1 in
+class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
+               dag InputDag = (ins IntRegs:$Rs)>
+  : JRInst<(outs), InputDag,
+      !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
+                                 "if ($Pu) callr $Rs"),
+                                 "callr $Rs"),
+      [], "", J_tc_2early_SLOT2> {
+    bits<5> Rs;
+    bits<2> Pu;
+    let isPredicated = isPred;
+    let isPredicatedFalse = isPredNot;
+
+    let IClass = 0b0101;
+    let Inst{27-25} = 0b000;
+    let Inst{24-23} = !if (isPred, 0b10, 0b01);
+    let Inst{22} = 0;
+    let Inst{21} = isPredNot;
+    let Inst{9-8} = !if (isPred, Pu, 0b00);
+    let Inst{20-16} = Rs;
+
+  }
+
+let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in {
+  def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
+  def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
+}
+
 let isTerminator = 1, hasSideEffects = 0 in {
 let isBranch = 1 in
 defm JMP : JMP_base<"JMP">, PredNewRel;

Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td?rev=223933&r1=223932&r2=223933&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td Wed Dec 10 12:24:16 2014
@@ -145,6 +145,14 @@ def CRRegs : RegisterClass<"Hexagon", [i
   let Size = 32;
 }
 
+def VolatileV3 {
+  list<Register> Regs = [D0, D1, D2, D3, D4, D5, D6, D7,
+                         R28, R31,
+                         P0, P1, P2, P3,
+                         M0, M1,
+                         LC0, LC1, SA0, SA1, USR_OVF];
+}
+
 def PositiveHalfWord : PatLeaf<(i32 IntRegs:$a),
 [{
   return isPositiveHalfWord(N);

Added: llvm/trunk/test/MC/Disassembler/Hexagon/jr.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/jr.txt?rev=223933&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/jr.txt (added)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/jr.txt Wed Dec 10 12:24:16 2014
@@ -0,0 +1,6 @@
+# RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
+
+0x00 0xc1 0x15 0x51
+# CHECK: if (p1) callr r21
+0x00 0xc3 0x35 0x51
+# CHECK: if (!p3) callr r21