[llvm] r223800 - [Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.
Colin LeMahieu
colinl at codeaurora.org
Tue Dec 9 10:16:50 PST 2014
Author: colinl
Date: Tue Dec 9 12:16:49 2014
New Revision: 223800
URL: http://llvm.org/viewvc/llvm-project?rev=223800&view=rev
Log:
[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt
llvm/trunk/test/MC/Hexagon/inst_cmp_eq.ll
llvm/trunk/test/MC/Hexagon/inst_cmp_eqi.ll
llvm/trunk/test/MC/Hexagon/inst_cmp_gt.ll
llvm/trunk/test/MC/Hexagon/inst_cmp_gti.ll
llvm/trunk/test/MC/Hexagon/inst_cmp_lt.ll
llvm/trunk/test/MC/Hexagon/inst_cmp_ugt.ll
llvm/trunk/test/MC/Hexagon/inst_cmp_ugti.ll
llvm/trunk/test/MC/Hexagon/inst_cmp_ult.ll
llvm/trunk/test/MC/Hexagon/inst_select.ll
Modified: llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp?rev=223800&r1=223799&r2=223800&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp Tue Dec 9 12:16:49 2014
@@ -103,7 +103,7 @@ bool HexagonExpandPredSpillCode::runOnMa
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_add),
HEXAGON_RESERVED_REG_1)
.addReg(FP).addReg(HEXAGON_RESERVED_REG_1);
- BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
+ BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr),
HEXAGON_RESERVED_REG_2).addReg(SrcReg);
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::STriw_indexed))
@@ -112,7 +112,7 @@ bool HexagonExpandPredSpillCode::runOnMa
} else {
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
- BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
+ BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr),
HEXAGON_RESERVED_REG_2).addReg(SrcReg);
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::STriw_indexed))
@@ -121,7 +121,7 @@ bool HexagonExpandPredSpillCode::runOnMa
.addReg(HEXAGON_RESERVED_REG_2);
}
} else {
- BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
+ BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr),
HEXAGON_RESERVED_REG_2).addReg(SrcReg);
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::STriw_indexed)).
@@ -154,7 +154,7 @@ bool HexagonExpandPredSpillCode::runOnMa
HEXAGON_RESERVED_REG_2)
.addReg(HEXAGON_RESERVED_REG_1)
.addImm(0);
- BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs),
+ BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp),
DstReg).addReg(HEXAGON_RESERVED_REG_2);
} else {
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
@@ -163,13 +163,13 @@ bool HexagonExpandPredSpillCode::runOnMa
HEXAGON_RESERVED_REG_2)
.addReg(HEXAGON_RESERVED_REG_1)
.addImm(0);
- BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs),
+ BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp),
DstReg).addReg(HEXAGON_RESERVED_REG_2);
}
} else {
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),
HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offset);
- BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs),
+ BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp),
DstReg).addReg(HEXAGON_RESERVED_REG_2);
}
MII = MBB->erase(MI);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=223800&r1=223799&r2=223800&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Tue Dec 9 12:16:49 2014
@@ -320,7 +320,7 @@ static unsigned doesIntrinsicContainPred
default:
return 0;
case Intrinsic::hexagon_C2_tfrpr:
- return Hexagon::TFR_RsPd;
+ return Hexagon::C2_tfrpr;
case Intrinsic::hexagon_C2_and:
return Hexagon::C2_and;
case Intrinsic::hexagon_C2_xor:
@@ -1177,7 +1177,7 @@ SDNode *HexagonDAGToDAGISel::SelectZeroE
if (N->getValueType(0) == MVT::i64) {
// Convert the zero_extend to Rs = Pd followed by COMBINE_rr(0,Rs).
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
- SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::TFR_RsPd, dl,
+ SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
MVT::i32,
SDValue(IsIntrinsic, 0));
SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::TFRI, dl,
@@ -1192,7 +1192,7 @@ SDNode *HexagonDAGToDAGISel::SelectZeroE
}
if (N->getValueType(0) == MVT::i32) {
// Convert the zero_extend to Rs = Pd
- SDNode* RsPd = CurDAG->getMachineNode(Hexagon::TFR_RsPd, dl,
+ SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
MVT::i32,
SDValue(IsIntrinsic, 0));
ReplaceUses(N, RsPd);
@@ -1236,7 +1236,7 @@ SDNode *HexagonDAGToDAGISel::SelectIntri
Ops.push_back(SDValue(Arg, 0));
} else if (RC == &Hexagon::PredRegsRegClass) {
// Do the transfer.
- SDNode *PdRs = CurDAG->getMachineNode(Hexagon::TFR_PdRs, dl, MVT::i1,
+ SDNode *PdRs = CurDAG->getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1,
SDValue(Arg, 0));
Ops.push_back(SDValue(PdRs,0));
} else if (!RC && (dyn_cast<ConstantSDNode>(Arg) != nullptr)) {
@@ -1293,7 +1293,7 @@ SDNode *HexagonDAGToDAGISel::SelectConst
CurDAG->getTargetConstant(0, MVT::i32));
// Pd = IntReg
- SDNode* Pd = CurDAG->getMachineNode(Hexagon::TFR_PdRs, dl, MVT::i1,
+ SDNode* Pd = CurDAG->getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1,
SDValue(IntRegTFR, 0));
// not(Pd)
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=223800&r1=223799&r2=223800&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Tue Dec 9 12:16:49 2014
@@ -454,13 +454,13 @@ void HexagonInstrInfo::copyPhysReg(Machi
}
if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
Hexagon::IntRegsRegClass.contains(DestReg)) {
- BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg).
+ BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
addReg(SrcReg, getKillRegState(KillSrc));
return;
}
if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
Hexagon::PredRegsRegClass.contains(DestReg)) {
- BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg).
+ BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
addReg(SrcReg, getKillRegState(KillSrc));
return;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=223800&r1=223799&r2=223800&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Tue Dec 9 12:16:49 2014
@@ -893,11 +893,6 @@ def TSTBIT_rr : SInst<(outs PredRegs:$ds
[(set (i1 PredRegs:$dst),
(setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
-def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
- "$dst = tstbit($src1, $src2)",
- [(set (i1 PredRegs:$dst),
- (setne (and (shl 1, (u5ImmPred:$src2)), (i32 IntRegs:$src1)), 0))]>;
-
//===----------------------------------------------------------------------===//
// ALU32/PRED -
//===----------------------------------------------------------------------===//
@@ -2216,6 +2211,7 @@ def SXTW : ALU64_rr<(outs DoubleRegs:$ds
//===----------------------------------------------------------------------===//
// STYPE/BIT +
//===----------------------------------------------------------------------===//
+
// clrbit.
def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
"$dst = clrbit($src1, #$src2)",
@@ -2259,15 +2255,66 @@ def TOGBIT_31 : ALU64_rr<(outs IntRegs:$
def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
(TOGBIT_31 (i32 IntRegs:$src1), 31)>;
+//===----------------------------------------------------------------------===//
+// STYPE/BIT -
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// STYPE/PRED +
+//===----------------------------------------------------------------------===//
+
// Predicate transfer.
+let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
+def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
+ "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> {
+ bits<5> Rd;
+ bits<2> Ps;
+
+ let IClass = 0b1000;
+ let Inst{27-24} = 0b1001;
+ let Inst{22} = 0b1;
+ let Inst{17-16} = Ps;
+ let Inst{4-0} = Rd;
+}
+
+// Transfer general register to predicate.
+let hasSideEffects = 0, isCodeGenOnly = 0 in
+def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
+ "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> {
+ bits<2> Pd;
+ bits<5> Rs;
+
+ let IClass = 0b1000;
+ let Inst{27-21} = 0b0101010;
+ let Inst{20-16} = Rs;
+ let Inst{1-0} = Pd;
+}
+
let hasSideEffects = 0 in
-def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
- "$dst = $src1 /* Should almost never emit this. */",
- []>;
-
-def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
- "$dst = $src1 /* Should almost never emit this. */",
- [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
+class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
+ : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
+ "$Pd = "#MnOp#"($Rs, #$u5)",
+ [], "", S_2op_tc_2early_SLOT23> {
+ bits<2> Pd;
+ bits<5> Rs;
+ bits<5> u5;
+ let IClass = 0b1000;
+ let Inst{27-24} = 0b0101;
+ let Inst{23-21} = MajOp;
+ let Inst{20-16} = Rs;
+ let Inst{13} = 0;
+ let Inst{12-8} = u5;
+ let Inst{1-0} = Pd;
+}
+
+def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
+
+let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
+ def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
+ (S2_tstbit_i IntRegs:$Rs, 0)>;
+}
+
+
//===----------------------------------------------------------------------===//
// STYPE/PRED -
//===----------------------------------------------------------------------===//
@@ -2840,7 +2887,7 @@ def : Pat <(select (i1 PredRegs:$src1),
// Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
def : Pat<(i1 (load ADDRriS11_2:$addr)),
- (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
+ (i1 (C2_tfrrp (i32 (LDrib ADDRriS11_2:$addr))))>;
// Map for truncating from 64 immediates to 32 bit immediates.
def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
@@ -2848,7 +2895,7 @@ def : Pat<(i32 (trunc (i64 DoubleRegs:$s
// Map for truncating from i64 immediates to i1 bit immediates.
def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
- (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
+ (i1 (C2_tfrrp (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
subreg_loreg))))>;
// Map memb(Rs) = Rdd -> memb(Rs) = Rt.
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=223800&r1=223799&r2=223800&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Tue Dec 9 12:16:49 2014
@@ -3016,7 +3016,7 @@ def : Pat <(i64 (load (HexagonCONST32_GP
// Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
let AddedComplexity = 100 in
def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
- (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>;
+ (i1 (C2_tfrrp (i32 (LDb_GP_V4 tglobaladdr:$global))))>;
// When the Interprocedural Global Variable optimizer realizes that a certain
// global variable takes only two constant values, it shrinks the global to
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt?rev=223800&r1=223799&r2=223800&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt Tue Dec 9 12:16:49 2014
@@ -8,5 +8,9 @@
# CHECK: p3 = cmp.gtu(r21:20, r31:30)
0x10 0xc3 0x00 0x86
# CHECK: r17:16 = mask(p3)
+0x03 0xc0 0x45 0x85
+# CHECK: p3 = r5
+0x05 0xc0 0x43 0x89
+# CHECK: r5 = p3
0x11 0xc2 0x03 0x89
# CHECK: r17 = vitpack(p3, p2)
\ No newline at end of file
Modified: llvm/trunk/test/MC/Hexagon/inst_cmp_eq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/inst_cmp_eq.ll?rev=223800&r1=223799&r2=223800&view=diff
==============================================================================
--- llvm/trunk/test/MC/Hexagon/inst_cmp_eq.ll (original)
+++ llvm/trunk/test/MC/Hexagon/inst_cmp_eq.ll Tue Dec 9 12:16:49 2014
@@ -7,4 +7,4 @@ define i1 @foo (i32 %a, i32 %b)
ret i1 %1
}
-; CHECK: 0000 004100f2 00400000 00c09f52
+; CHECK: 0000 004100f2 00404089 00c09f52
Modified: llvm/trunk/test/MC/Hexagon/inst_cmp_eqi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/inst_cmp_eqi.ll?rev=223800&r1=223799&r2=223800&view=diff
==============================================================================
--- llvm/trunk/test/MC/Hexagon/inst_cmp_eqi.ll (original)
+++ llvm/trunk/test/MC/Hexagon/inst_cmp_eqi.ll Tue Dec 9 12:16:49 2014
@@ -7,4 +7,4 @@ define i1 @foo (i32 %a)
ret i1 %1
}
-; CHECK: 0000 40450075 00400000 00c09f52
+; CHECK: 0000 40450075 00404089 00c09f52
Modified: llvm/trunk/test/MC/Hexagon/inst_cmp_gt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/inst_cmp_gt.ll?rev=223800&r1=223799&r2=223800&view=diff
==============================================================================
--- llvm/trunk/test/MC/Hexagon/inst_cmp_gt.ll (original)
+++ llvm/trunk/test/MC/Hexagon/inst_cmp_gt.ll Tue Dec 9 12:16:49 2014
@@ -7,4 +7,4 @@ define i1 @foo (i32 %a, i32 %b)
ret i1 %1
}
-; CHECK: 0000 004140f2 00400000 00c09f52
+; CHECK: 0000 004140f2 00404089 00c09f52
Modified: llvm/trunk/test/MC/Hexagon/inst_cmp_gti.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/inst_cmp_gti.ll?rev=223800&r1=223799&r2=223800&view=diff
==============================================================================
--- llvm/trunk/test/MC/Hexagon/inst_cmp_gti.ll (original)
+++ llvm/trunk/test/MC/Hexagon/inst_cmp_gti.ll Tue Dec 9 12:16:49 2014
@@ -7,4 +7,4 @@ define i1 @foo (i32 %a)
ret i1 %1
}
-; CHECK: 0000 40454075 00400000 00c09f52
+; CHECK: 0000 40454075 00404089 00c09f52
Modified: llvm/trunk/test/MC/Hexagon/inst_cmp_lt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/inst_cmp_lt.ll?rev=223800&r1=223799&r2=223800&view=diff
==============================================================================
--- llvm/trunk/test/MC/Hexagon/inst_cmp_lt.ll (original)
+++ llvm/trunk/test/MC/Hexagon/inst_cmp_lt.ll Tue Dec 9 12:16:49 2014
@@ -7,4 +7,4 @@ define i1 @foo (i32 %a, i32 %b)
ret i1 %1
}
-; CHECK: 0000 004041f2 00400000 00c09f52
+; CHECK: 0000 004041f2 00404089 00c09f52
Modified: llvm/trunk/test/MC/Hexagon/inst_cmp_ugt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/inst_cmp_ugt.ll?rev=223800&r1=223799&r2=223800&view=diff
==============================================================================
--- llvm/trunk/test/MC/Hexagon/inst_cmp_ugt.ll (original)
+++ llvm/trunk/test/MC/Hexagon/inst_cmp_ugt.ll Tue Dec 9 12:16:49 2014
@@ -7,4 +7,4 @@ define i1 @foo (i32 %a, i32 %b)
ret i1 %1
}
-; CHECK: 0000 004160f2 00400000 00c09f52
+; CHECK: 0000 004160f2 00404089 00c09f52
Modified: llvm/trunk/test/MC/Hexagon/inst_cmp_ugti.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/inst_cmp_ugti.ll?rev=223800&r1=223799&r2=223800&view=diff
==============================================================================
--- llvm/trunk/test/MC/Hexagon/inst_cmp_ugti.ll (original)
+++ llvm/trunk/test/MC/Hexagon/inst_cmp_ugti.ll Tue Dec 9 12:16:49 2014
@@ -7,4 +7,4 @@ define i1 @foo (i32 %a)
ret i1 %1
}
-; CHECK: 0000 40458075 00400000 00c09f52
+; CHECK: 0000 40458075 00404089 00c09f52
Modified: llvm/trunk/test/MC/Hexagon/inst_cmp_ult.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/inst_cmp_ult.ll?rev=223800&r1=223799&r2=223800&view=diff
==============================================================================
--- llvm/trunk/test/MC/Hexagon/inst_cmp_ult.ll (original)
+++ llvm/trunk/test/MC/Hexagon/inst_cmp_ult.ll Tue Dec 9 12:16:49 2014
@@ -7,4 +7,4 @@ define i1 @foo (i32 %a, i32 %b)
ret i1 %1
}
-; CHECK: 0000 004061f2 00400000 00c09f52
+; CHECK: 0000 004061f2 00404089 00c09f52
Modified: llvm/trunk/test/MC/Hexagon/inst_select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/inst_select.ll?rev=223800&r1=223799&r2=223800&view=diff
==============================================================================
--- llvm/trunk/test/MC/Hexagon/inst_select.ll (original)
+++ llvm/trunk/test/MC/Hexagon/inst_select.ll Tue Dec 9 12:16:49 2014
@@ -7,4 +7,4 @@ define i32 @foo (i1 %a, i32 %b, i32 %c)
ret i32 %1
}
-; CHECK: 0000 00400000 004201f4 00c09f52
+; CHECK: 0000 00400085 004201f4 00c09f52
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