[llvm] r223769 - [x86] Bring some sanity to the x86 CPU processor definitions.
Hal Finkel
hfinkel at anl.gov
Tue Dec 9 03:21:20 PST 2014
----- Original Message -----
> From: "Chandler Carruth" <chandlerc at gmail.com>
> To: llvm-commits at cs.uiuc.edu
> Sent: Tuesday, December 9, 2014 4:58:37 AM
> Subject: [llvm] r223769 - [x86] Bring some sanity to the x86 CPU processor definitions.
>
> Author: chandlerc
> Date: Tue Dec 9 04:58:36 2014
> New Revision: 223769
>
> URL: http://llvm.org/viewvc/llvm-project?rev=223769&view=rev
> Log:
> [x86] Bring some sanity to the x86 CPU processor definitions.
>
> Notably, this adds simple micro-architecture names for the Intel CPU
> variants, and defines the old 'core'-based names as aliases. GCC has
> started to simplify their documented interface to use these names as
> well, so it seems like we can start to converge on a consistent
> pattern.
>
> I'd appreciate Intel double checking the entries that aren't yet
> documented widely, especially Atom (Bonnell and Silvermont), Knights
> Landing,
Indeed, as Intel has announced that Knights Landing will use Silvermont cores (http://newsroom.intel.com/community/intel_newsroom/blog/2014/06/23/intel-re-architects-the-fundamental-building-block-for-high-performance-computing), I'd think that its processor definition should use SLMModel, etc. instead of HaswellModel.
-Hal
> and Skylake. But this change shouldn't break any existing
> users.
>
> Also, ran clang-format to re-format this code and it actually worked
> (modulo a tiny bug) so hopefully we can start to stop thinking about
> formatting this stuff.
>
> Modified:
> llvm/trunk/lib/Target/X86/X86.td
>
> Modified: llvm/trunk/lib/Target/X86/X86.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=223769&r1=223768&r2=223769&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86.td (original)
> +++ llvm/trunk/lib/Target/X86/X86.td Tue Dec 9 04:58:36 2014
> @@ -240,82 +240,155 @@ def : ProcessorModel<"core2", SandyBridg
> def : ProcessorModel<"penryn", SandyBridgeModel,
> [FeatureSSE41, FeatureCMPXCHG16B,
> FeatureSlowBTMem]>;
>
> -// Atom.
> -def : ProcessorModel<"atom", AtomModel,
> - [ProcIntelAtom, FeatureSSSE3,
> FeatureCMPXCHG16B,
> - FeatureMOVBE, FeatureSlowBTMem,
> FeatureLeaForSP,
> - FeatureSlowDivide32, FeatureSlowDivide64,
> - FeatureCallRegIndirect,
> - FeatureLEAUsesAG,
> - FeaturePadShortFunctions]>;
> -
> -// Atom Silvermont.
> -def : ProcessorModel<"slm", SLMModel, [ProcIntelSLM,
> - FeatureSSE42, FeatureCMPXCHG16B,
> - FeatureMOVBE, FeaturePOPCNT,
> - FeaturePCLMUL, FeatureAES,
> - FeatureSlowDivide64,
> - FeatureCallRegIndirect,
> - FeaturePRFCHW,
> - FeatureSlowLEA, FeatureSlowIncDec,
> - FeatureSlowBTMem, FeatureFastUAMem]>;
> +// Atom CPUs.
> +class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
> + ProcIntelAtom,
> + FeatureSSSE3,
> + FeatureCMPXCHG16B,
> + FeatureMOVBE,
> + FeatureSlowBTMem,
> + FeatureLeaForSP,
> + FeatureSlowDivide32,
> + FeatureSlowDivide64,
> + FeatureCallRegIndirect,
> + FeatureLEAUsesAG,
> + FeaturePadShortFunctions
> + ]>;
> +def : BonnellProc<"bonnell">;
> +def : BonnellProc<"atom">; // Pin the generic name to the baseline.
> +
> +class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
> + ProcIntelSLM,
> + FeatureSSE42,
> + FeatureCMPXCHG16B,
> + FeatureMOVBE,
> + FeaturePOPCNT,
> + FeaturePCLMUL,
> + FeatureAES,
> + FeatureSlowDivide64,
> + FeatureCallRegIndirect,
> + FeaturePRFCHW,
> + FeatureSlowLEA,
> + FeatureSlowIncDec,
> + FeatureSlowBTMem,
> + FeatureFastUAMem
> + ]>;
> +def : SilvermontProc<"silvermont">;
> +def : SilvermontProc<"slm">; // Legacy alias.
> +
> // "Arrandale" along with corei3 and corei5
> -def : ProcessorModel<"corei7", SandyBridgeModel,
> - [FeatureSSE42, FeatureCMPXCHG16B,
> FeatureSlowBTMem,
> - FeatureFastUAMem, FeaturePOPCNT, FeatureAES]>;
> -
> -def : ProcessorModel<"nehalem", SandyBridgeModel,
> - [FeatureSSE42, FeatureCMPXCHG16B,
> FeatureSlowBTMem,
> - FeatureFastUAMem, FeaturePOPCNT]>;
> +class NehalemProc<string Name, list<SubtargetFeature>
> AdditionalFeatures>
> + : ProcessorModel<Name, SandyBridgeModel, !listconcat([
> +
> FeatureSSE42,
> +
> FeatureCMPXCHG16B,
> +
> FeatureSlowBTMem,
> +
> FeatureFastUAMem,
> +
> FeaturePOPCNT
> + ],
> +
> AdditionalFeatures)>;
> +def : NehalemProc<"nehalem", []>;
> +def : NehalemProc<"corei7", [FeatureAES]>;
> +
> // Westmere is a similar machine to nehalem with some additional
> features.
> // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
> -def : ProcessorModel<"westmere", SandyBridgeModel,
> - [FeatureSSE42, FeatureCMPXCHG16B,
> FeatureSlowBTMem,
> - FeatureFastUAMem, FeaturePOPCNT, FeatureAES,
> - FeaturePCLMUL]>;
> -// Sandy Bridge
> +class WestmereProc<string Name> : ProcessorModel<Name,
> SandyBridgeModel, [
> + FeatureSSE42,
> + FeatureCMPXCHG16B,
> + FeatureSlowBTMem,
> + FeatureFastUAMem,
> + FeaturePOPCNT,
> + FeatureAES,
> + FeaturePCLMUL
> + ]>;
> +def : WestmereProc<"westmere">;
> +
> // SSE is not listed here since llvm treats AVX as a
> reimplementation of SSE,
> // rather than a superset.
> -def : ProcessorModel<"corei7-avx", SandyBridgeModel,
> - [FeatureAVX, FeatureCMPXCHG16B,
> FeatureFastUAMem,
> - FeatureSlowUAMem32, FeaturePOPCNT, FeatureAES,
> - FeaturePCLMUL]>;
> -// Ivy Bridge
> -def : ProcessorModel<"core-avx-i", SandyBridgeModel,
> - [FeatureAVX, FeatureCMPXCHG16B,
> FeatureFastUAMem,
> - FeatureSlowUAMem32, FeaturePOPCNT, FeatureAES,
> - FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
> - FeatureFSGSBase]>;
> -
> -// Haswell
> -def : ProcessorModel<"core-avx2", HaswellModel,
> - [FeatureAVX2, FeatureCMPXCHG16B,
> FeatureFastUAMem,
> - FeaturePOPCNT, FeatureAES, FeaturePCLMUL,
> FeatureRDRAND,
> - FeatureF16C, FeatureFSGSBase, FeatureMOVBE,
> FeatureLZCNT,
> - FeatureBMI, FeatureBMI2, FeatureFMA,
> FeatureRTM,
> - FeatureHLE, FeatureSlowIncDec]>;
> -
> -// Broadwell
> -def : ProcessorModel<"broadwell", HaswellModel,
> - [FeatureAVX2, FeatureCMPXCHG16B,
> FeatureFastUAMem,
> - FeaturePOPCNT, FeatureAES, FeaturePCLMUL,
> FeatureRDRAND,
> - FeatureF16C, FeatureFSGSBase, FeatureMOVBE,
> FeatureLZCNT,
> - FeatureBMI, FeatureBMI2, FeatureFMA,
> FeatureRTM,
> - FeatureHLE, FeatureADX, FeatureRDSEED,
> FeatureSMAP,
> - FeatureSlowIncDec]>;
> -// KNL
> +class SandyBridgeProc<string Name> : ProcessorModel<Name,
> SandyBridgeModel, [
> + FeatureAVX,
> + FeatureCMPXCHG16B,
> + FeatureFastUAMem,
> + FeatureSlowUAMem32,
> + FeaturePOPCNT,
> + FeatureAES,
> + FeaturePCLMUL
> + ]>;
> +def : SandyBridgeProc<"sandybridge">;
> +def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
> +
> +class IvyBridgeProc<string Name> : ProcessorModel<Name,
> SandyBridgeModel, [
> + FeatureAVX,
> + FeatureCMPXCHG16B,
> + FeatureFastUAMem,
> + FeatureSlowUAMem32,
> + FeaturePOPCNT,
> + FeatureAES,
> + FeaturePCLMUL,
> + FeatureRDRAND,
> + FeatureF16C,
> + FeatureFSGSBase
> + ]>;
> +def : IvyBridgeProc<"ivybridge">;
> +def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
> +
> +class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel,
> [
> + FeatureAVX2,
> + FeatureCMPXCHG16B,
> + FeatureFastUAMem,
> + FeaturePOPCNT,
> + FeatureAES,
> + FeaturePCLMUL,
> + FeatureRDRAND,
> + FeatureF16C,
> + FeatureFSGSBase,
> + FeatureMOVBE,
> + FeatureLZCNT,
> + FeatureBMI,
> + FeatureBMI2,
> + FeatureFMA,
> + FeatureRTM,
> + FeatureHLE,
> + FeatureSlowIncDec
> + ]>;
> +def : HaswellProc<"haswell">;
> +def : HaswellProc<"core-avx2">; // Legacy alias.
> +
> +class BroadwellProc<string Name> : ProcessorModel<Name,
> HaswellModel, [
> + FeatureAVX2,
> + FeatureCMPXCHG16B,
> + FeatureFastUAMem,
> + FeaturePOPCNT,
> + FeatureAES,
> + FeaturePCLMUL,
> + FeatureRDRAND,
> + FeatureF16C,
> + FeatureFSGSBase,
> + FeatureMOVBE,
> + FeatureLZCNT,
> + FeatureBMI,
> + FeatureBMI2,
> + FeatureFMA,
> + FeatureRTM,
> + FeatureHLE,
> + FeatureADX,
> + FeatureRDSEED,
> + FeatureSMAP,
> + FeatureSlowIncDec
> + ]>;
> +def : BroadwellProc<"broadwell">;
> +
> // FIXME: define KNL model
> -def : ProcessorModel<"knl", HaswellModel,
> +class KnightsLandingProc<string Name> : ProcessorModel<Name,
> HaswellModel,
> [FeatureAVX512, FeatureERI, FeatureCDI,
> FeaturePFI,
> FeatureCMPXCHG16B, FeatureFastUAMem,
> FeaturePOPCNT,
> FeatureAES, FeaturePCLMUL, FeatureRDRAND,
> FeatureF16C,
> FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
> FeatureBMI,
> FeatureBMI2, FeatureFMA, FeatureRTM,
> FeatureHLE,
> FeatureSlowIncDec]>;
> +def : KnightsLandingProc<"knl">;
>
> -// SKX
> // FIXME: define SKX model
> -def : ProcessorModel<"skx", HaswellModel,
> +class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
> [FeatureAVX512, FeatureCDI,
> FeatureDQI, FeatureBWI, FeatureVLX,
> FeatureCMPXCHG16B, FeatureFastUAMem,
> FeaturePOPCNT,
> @@ -323,6 +396,11 @@ def : ProcessorModel<"skx", HaswellModel
> FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
> FeatureBMI,
> FeatureBMI2, FeatureFMA, FeatureRTM,
> FeatureHLE,
> FeatureSlowIncDec, FeatureSGX]>;
> +def : SkylakeProc<"skylake">;
> +def : SkylakeProc<"skx">; // Legacy alias.
> +
> +
> +// AMD CPUs.
>
> def : Proc<"k6", [FeatureMMX]>;
> def : Proc<"k6-2", [Feature3DNow]>;
>
>
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--
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory
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