[llvm] r223664 - [Hexagon] Adding packhl instruction.

[Colin LeMahieu]

Author: colinl
Date: Mon Dec  8 11:01:18 2014
New Revision: 223664

URL: http://llvm.org/viewvc/llvm-project?rev=223664&view=rev
Log:
[Hexagon] Adding packhl instruction.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
    llvm/trunk/test/MC/Disassembler/Hexagon/alu32_perm.txt

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=223664&r1=223663&r2=223664&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Mon Dec  8 11:01:18 2014
@@ -204,6 +204,12 @@ def: BinOp32_pat<or,  A2_or,  i32>;
 def: BinOp32_pat<sub, A2_sub, i32>;
 def: BinOp32_pat<xor, A2_xor, i32>;
 
+// A few special cases producing register pairs:
+let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0,
+    isCodeGenOnly = 0 in {
+  def S2_packhl    : T_ALU32_3op  <"packhl",  0b101, 0b100, 0, 0>;
+}
+
 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg"  in
 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
   : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),

Modified: llvm/trunk/test/MC/Disassembler/Hexagon/alu32_perm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/alu32_perm.txt?rev=223664&r1=223663&r2=223664&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/alu32_perm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/alu32_perm.txt Mon Dec  8 11:01:18 2014
@@ -22,3 +22,5 @@
 # CHECK: r17 = aslh(r21)
 0x11 0xc0 0x35 0x70
 # CHECK: r17 = asrh(r21)
+0x10 0xdf 0x95 0xf5
+# CHECK: r17:16 = packhl(r21, r31)