[PATCH] [X86][SSE] Keep 4i32 vector insertions in integer domain on pre-SSE4.1 targets

[Simon Pilgrim]

Added X86vzmovl folded loads tests.

I looked at using a pand with a constant mask as an alternative and saw a minimal regression (nearly in the noise) compared to the movq/movss versions I was already testing against. I'm worried about pursuing that route though - it adds addiitonal memory access and the mask approach might make it more difficult for future optimizations of the multiple pshufd ops that are still in the vector-shuffle-128-v4.ll tests.

http://reviews.llvm.org/D6526

Files:
  lib/Target/X86/X86InstrSSE.td
  test/CodeGen/X86/lower-vec-shift-2.ll
  test/CodeGen/X86/uint_to_fp-2.ll
  test/CodeGen/X86/vector-shuffle-128-v4.ll
  test/CodeGen/X86/vector-zmov.ll
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