[llvm] r223334 - [Hexagon] Marking some instructions as CodeGenOnly=0 and adding disassembly tests.

[Colin LeMahieu]

Author: colinl
Date: Wed Dec  3 21:41:21 2014
New Revision: 223334

URL: http://llvm.org/viewvc/llvm-project?rev=223334&view=rev
Log:
[Hexagon] Marking some instructions as CodeGenOnly=0 and adding disassembly tests.

Added:
    llvm/trunk/test/MC/Disassembler/Hexagon/
    llvm/trunk/test/MC/Disassembler/Hexagon/alu32_alu.txt
Modified:
    llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
    llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td

Modified: llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp?rev=223334&r1=223333&r2=223334&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp Wed Dec  3 21:41:21 2014
@@ -8,6 +8,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/HexagonBaseInfo.h"
+#include "MCTargetDesc/HexagonMCInst.h"
 #include "MCTargetDesc/HexagonMCTargetDesc.h"
 
 #include "llvm/MC/MCContext.h"
@@ -110,5 +111,7 @@ DecodeStatus HexagonDisassembler::getIns
 
   // Remove parse bits.
   insn &= ~static_cast<uint32_t>(HexagonII::InstParseBits::INST_PARSE_MASK);
-  return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);
+  DecodeStatus Result = decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);
+  HexagonMCInst::AppendImplicitOperands(MI);
+  return Result;
 }

Modified: llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt?rev=223334&r1=223333&r2=223334&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt (original)
+++ llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt Wed Dec  3 21:41:21 2014
@@ -19,5 +19,5 @@
 type = Library
 name = HexagonDisassembler
 parent = Hexagon
-required_libraries = HexagonInfo MCDisassembler Support
+required_libraries = HexagonDesc HexagonInfo MCDisassembler Support
 add_to_library_groups = Hexagon

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=223334&r1=223333&r2=223334&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Wed Dec  3 21:41:21 2014
@@ -170,12 +170,13 @@ multiclass T_ALU32_3op_A2<string mnemoni
   defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
 }
 
-let isCodeGenOnly = 0 in
+let isCodeGenOnly = 0 in {
 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
 defm or  : T_ALU32_3op_A2<"or",  0b001, 0b001, 0, 1>;
 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
+}
 
 // Pats for instruction selection.
 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
@@ -275,11 +276,13 @@ multiclass ALU32_2op_base<string mnemoni
   }
 }
 
+let isCodeGenOnly = 0 in {
 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
 defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
+}
 
 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has

Added: llvm/trunk/test/MC/Disassembler/Hexagon/alu32_alu.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/alu32_alu.txt?rev=223334&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/alu32_alu.txt (added)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/alu32_alu.txt Wed Dec  3 21:41:21 2014
@@ -0,0 +1,18 @@
+# XFAIL: arm-windows
+# XFAIL: arm-linux
+# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+
+0x11 0xdf 0x15 0xf3
+# CHECK: r17 = add(r21, r31)
+0x11 0xdf 0x15 0xf1
+# CHECK: r17 = and(r21, r31)
+0x11 0xdf 0x35 0xf1
+# CHECK: r17 = or(r21, r31)
+0x11 0xdf 0x75 0xf1
+# CHECK: r17 = xor(r21, r31)
+0x11 0xdf 0x35 0xf3
+# CHECK: r17 = sub(r31, r21)
+0x11 0xc0 0xbf 0x70
+# CHECK: r17 = sxtb(r31)
+0x11 0xc0 0xd5 0x70
+# CHECK: r17 = zxth(r21)