[PATCH 3/3] R600/SI: Remove isDS InstrMapping, use TSFlags instead

[Matt Arsenault]

> On Dec 1, 2014, at 9:12 AM, Marek Olšák <maraeo at gmail.com> wrote:
> 
> Okay. What about patches 1 and 2?
> 
> Marek

I don’t see those

-Matt




> 
> On Fri, Nov 28, 2014 at 5:02 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>> 
>> On Nov 28, 2014, at 8:07 AM, Marek Olšák <maraeo at gmail.com> wrote:
>> 
>> From: Marek Olšák <marek.olsak at amd.com>
>> 
>> InstrMapping was causing TableGen crashes with multi classes.
>> 
>> 
>> 
>> Actually I posted a patch which does exactly this (plus some other cleanups)
>> here:
>> 
>> http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20141124/246167.html
>> in 0002-R600-SI-Various-instruction-format-bit-test-cleanups.patch
>> 
>> 
>> 
>> ---
>> lib/Target/R600/SIDefines.h       |  3 ++-
>> lib/Target/R600/SIInstrFormats.td |  3 +++
>> lib/Target/R600/SIInstrInfo.cpp   | 10 +---------
>> lib/Target/R600/SIInstrInfo.td    |  8 --------
>> 4 files changed, 6 insertions(+), 18 deletions(-)
>> 
>> diff --git a/lib/Target/R600/SIDefines.h b/lib/Target/R600/SIDefines.h
>> index 2e7dab6..36285c7 100644
>> --- a/lib/Target/R600/SIDefines.h
>> +++ b/lib/Target/R600/SIDefines.h
>> @@ -23,7 +23,8 @@ enum {
>>  SALU = 1 << 9,
>>  MUBUF = 1 << 10,
>>  MTBUF = 1 << 11,
>> -  FLAT = 1 << 12
>> +  FLAT = 1 << 12,
>> +  DS = 1 << 13
>> };
>> }
>> 
>> diff --git a/lib/Target/R600/SIInstrFormats.td
>> b/lib/Target/R600/SIInstrFormats.td
>> index 0fbce35..0f95518 100644
>> --- a/lib/Target/R600/SIInstrFormats.td
>> +++ b/lib/Target/R600/SIInstrFormats.td
>> @@ -27,6 +27,7 @@ class InstSI <dag outs, dag ins, string asm, list<dag>
>> pattern> :
>>  field bits<1> MUBUF = 0;
>>  field bits<1> MTBUF = 0;
>>  field bits<1> FLAT = 0;
>> +  field bits<1> DS = 0;
>> 
>>  // These need to be kept in sync with the enum in SIInstrFlags.
>>  let TSFlags{0} = VM_CNT;
>> @@ -42,6 +43,7 @@ class InstSI <dag outs, dag ins, string asm, list<dag>
>> pattern> :
>>  let TSFlags{10} = MUBUF;
>>  let TSFlags{11} = MTBUF;
>>  let TSFlags{12} = FLAT;
>> +  let TSFlags{13} = DS;
>> 
>>  // Most instructions require adjustments after selection to satisfy
>>  // operand requirements.
>> @@ -544,6 +546,7 @@ let Uses = [EXEC] in {
>> class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
>>    InstSI <outs, ins, asm, pattern> , DSe<op> {
>> 
>> +  let DS = 1;
>>  let LGKM_CNT = 1;
>>  let UseNamedOperandTable = 1;
>>  let DisableEncoding = "$m0";
>> diff --git a/lib/Target/R600/SIInstrInfo.cpp
>> b/lib/Target/R600/SIInstrInfo.cpp
>> index 1a0010c..f71c580 100644
>> --- a/lib/Target/R600/SIInstrInfo.cpp
>> +++ b/lib/Target/R600/SIInstrInfo.cpp
>> @@ -895,16 +895,8 @@ bool
>> SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
>>  return false;
>> }
>> 
>> -namespace llvm {
>> -namespace AMDGPU {
>> -// Helper function generated by tablegen.  We are wrapping this with
>> -// an SIInstrInfo function that returns bool rather than int.
>> -int isDS(uint16_t Opcode);
>> -}
>> -}
>> -
>> bool SIInstrInfo::isDS(uint16_t Opcode) const {
>> -  return ::AMDGPU::isDS(Opcode) != -1;
>> +  return get(Opcode).TSFlags & SIInstrFlags::DS;
>> }
>> 
>> bool SIInstrInfo::isMIMG(uint16_t Opcode) const {
>> diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
>> index 392c272..cdbc22e 100644
>> --- a/lib/Target/R600/SIInstrInfo.td
>> +++ b/lib/Target/R600/SIInstrInfo.td
>> @@ -1497,14 +1497,6 @@ def getCommuteOrig : InstrMapping {
>>  let ValueCols = [["1"]];
>> }
>> 
>> -def isDS : InstrMapping {
>> -  let FilterClass = "DS";
>> -  let RowFields = ["Inst"];
>> -  let ColFields = ["Size"];
>> -  let KeyCol = ["8"];
>> -  let ValueCols = [["8"]];
>> -}
>> -
>> def getMCOpcode : InstrMapping {
>>  let FilterClass = "SIMCInstr";
>>  let RowFields = ["PseudoInstr"];
>> --
>> 2.1.0
>> 
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