[PATCH] [PowerPC] Add Power8 Instruction Scheduling Tablegen

[hfinkel at anl.gov]

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Comment at: lib/Target/PowerPC/PPCScheduleP8.td:46
@@ +45,3 @@
+// FPU, so keep in mind that FPU==VSU.
+// In contract to P7, the VMX units on P8 are symmetric, so no need to
+// split vector integer ops or 128-bit load/store/perms to the specific units.
----------------
contract to -> contrast to the

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Comment at: lib/Target/PowerPC/PPCScheduleP8.td:245
@@ +244,3 @@
+// Stores are dual-issued from the issue queue, so may only take up one
+// dispatch slot.  The instruction will be broken into two internal iops. The
+// agen op is issued to the LSU, and the data op (register fetch) is issued
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Assuming the i in ops stands for internal, internal iops seems somewhat redundant.

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Comment at: lib/Target/PowerPC/PPCScheduleP8.td:251
@@ +250,3 @@
+                                   InstrStage<1, [P8_LSU1, P8_LSU2]>,
+                                   InstrStage<1, [P8_LU1, P8_LU2],0>],
+                                  [1, 1, 1]>,
----------------
Having ,0> at the end of the last InstrStage does not look right. That optional last number means "how many cycles must we wait before moving on to the next dispatch stage". Putting it on the last stage does not mean anything. Does it belong on the stage before? (or is there really a 1 cycle delay between the when the iop is dispatched to the LU)

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Comment at: lib/Target/PowerPC/PPCScheduleP8.td:256
@@ +255,3 @@
+                                   InstrStage<1, [P8_LU1, P8_LU2,
+                                                  P8_LSU1, P8_LSU2], 0>]
+                                  [1, 1, 1]>,
----------------
Same here; ,0> in the last stage does not mean anything.

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Comment at: lib/Target/PowerPC/PPCScheduleP8.td:378
@@ +377,3 @@
+// P8 machine model for scheduling and other instruction cost heuristics.
+// P8 is 8 insn dispatch group (6 non-branch, 2 branch) and can issue up to
+// 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
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is -> has an

http://reviews.llvm.org/D6358