[llvm] r222846 - [Hexagon] Adding and64, or64, and xor64 instructions.

[Colin LeMahieu]

Author: colinl
Date: Wed Nov 26 12:55:59 2014
New Revision: 222846

URL: http://llvm.org/viewvc/llvm-project?rev=222846&view=rev
Log:
[Hexagon] Adding and64, or64, and xor64 instructions.

Added:
    llvm/trunk/test/MC/Hexagon/inst_and64.ll
    llvm/trunk/test/MC/Hexagon/inst_or64.ll
    llvm/trunk/test/MC/Hexagon/inst_xor64.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=222846&r1=222845&r2=222846&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Wed Nov 26 12:55:59 2014
@@ -701,6 +701,19 @@ def A2_subp : T_ALU64_arith<"sub", 0b001
 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
 
+class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
+                      bit IsNeg>
+  : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
+               !if(IsNeg,"~","")>;
+
+def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
+def A2_orp  : T_ALU64_logical<"or",  0b010, 0, 1, 0>;
+def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>;
+
+def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
+def: Pat<(i64 (or  I64:$Rs, I64:$Rt)), (A2_orp  I64:$Rs, I64:$Rt)>;
+def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
+
 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
 // that reverse the order of the operands.
 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;

Added: llvm/trunk/test/MC/Hexagon/inst_and64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/inst_and64.ll?rev=222846&view=auto
==============================================================================
--- llvm/trunk/test/MC/Hexagon/inst_and64.ll (added)
+++ llvm/trunk/test/MC/Hexagon/inst_and64.ll Wed Nov 26 12:55:59 2014
@@ -0,0 +1,10 @@
+;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
+;; RUN: | llvm-objdump -s - | FileCheck %s
+
+define i64 @foo (i64 %a, i64 %b)
+{
+  %1 = and i64 %a, %b
+  ret i64 %1
+}
+
+; CHECK:  0000 0042e0d3 00c09f52

Added: llvm/trunk/test/MC/Hexagon/inst_or64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/inst_or64.ll?rev=222846&view=auto
==============================================================================
--- llvm/trunk/test/MC/Hexagon/inst_or64.ll (added)
+++ llvm/trunk/test/MC/Hexagon/inst_or64.ll Wed Nov 26 12:55:59 2014
@@ -0,0 +1,10 @@
+;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
+;; RUN: | llvm-objdump -s - | FileCheck %s
+
+define i64 @foo (i64 %a, i64 %b)
+{
+  %1 = or i64 %a, %b
+  ret i64 %1
+}
+
+; CHECK:  0000 4042e0d3 00c09f52

Added: llvm/trunk/test/MC/Hexagon/inst_xor64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/inst_xor64.ll?rev=222846&view=auto
==============================================================================
--- llvm/trunk/test/MC/Hexagon/inst_xor64.ll (added)
+++ llvm/trunk/test/MC/Hexagon/inst_xor64.ll Wed Nov 26 12:55:59 2014
@@ -0,0 +1,10 @@
+;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
+;; RUN: | llvm-objdump -s - | FileCheck %s
+
+define i64 @foo (i64 %a, i64 %b)
+{
+  %1 = xor i64 %a, %b
+  ret i64 %1
+}
+
+; CHECK:  0000 8042e0d3 00c09f52