[llvm] r222801 - Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.
Tom Stellard
tom at stellard.net
Tue Nov 25 18:16:22 PST 2014
On Wed, Nov 26, 2014 at 12:46:26AM -0000, Craig Topper wrote:
> Author: ctopper
> Date: Tue Nov 25 18:46:26 2014
> New Revision: 222801
>
> URL: http://llvm.org/viewvc/llvm-project?rev=222801&view=rev
> Log:
> Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.
>
Thank you!
> Modified:
> llvm/trunk/include/llvm/Target/Target.td
> llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
> llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
> llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td
> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td
> llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td
> llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
> llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
> llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
> llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td
> llvm/trunk/lib/Target/NVPTX/NVPTXVector.td
> llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
> llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
> llvm/trunk/lib/Target/R600/R600Instructions.td
> llvm/trunk/lib/Target/R600/SIInstrFormats.td
> llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td
> llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
> llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
> llvm/trunk/lib/Target/X86/X86InstrCompiler.td
> llvm/trunk/lib/Target/X86/X86InstrExtension.td
> llvm/trunk/lib/Target/X86/X86InstrFMA.td
> llvm/trunk/lib/Target/X86/X86InstrFPStack.td
> llvm/trunk/lib/Target/X86/X86InstrInfo.td
> llvm/trunk/lib/Target/X86/X86InstrMMX.td
> llvm/trunk/lib/Target/X86/X86InstrSSE.td
> llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td
> llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td
>
> Modified: llvm/trunk/include/llvm/Target/Target.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/Target.td (original)
> +++ llvm/trunk/include/llvm/Target/Target.td Tue Nov 25 18:46:26 2014
> @@ -734,7 +734,7 @@ def INLINEASM : Instruction {
> let OutOperandList = (outs);
> let InOperandList = (ins variable_ops);
> let AsmString = "";
> - let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
> + let hasSideEffects = 0; // Note side effect is encoded in an operand.
> }
> def CFI_INSTRUCTION : Instruction {
> let OutOperandList = (outs);
> @@ -761,26 +761,26 @@ def KILL : Instruction {
> let OutOperandList = (outs);
> let InOperandList = (ins variable_ops);
> let AsmString = "";
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> }
> def EXTRACT_SUBREG : Instruction {
> let OutOperandList = (outs unknown:$dst);
> let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
> let AsmString = "";
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> }
> def INSERT_SUBREG : Instruction {
> let OutOperandList = (outs unknown:$dst);
> let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
> let AsmString = "";
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> let Constraints = "$supersrc = $dst";
> }
> def IMPLICIT_DEF : Instruction {
> let OutOperandList = (outs unknown:$dst);
> let InOperandList = (ins);
> let AsmString = "";
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> let isReMaterializable = 1;
> let isAsCheapAsAMove = 1;
> }
> @@ -788,33 +788,33 @@ def SUBREG_TO_REG : Instruction {
> let OutOperandList = (outs unknown:$dst);
> let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
> let AsmString = "";
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> }
> def COPY_TO_REGCLASS : Instruction {
> let OutOperandList = (outs unknown:$dst);
> let InOperandList = (ins unknown:$src, i32imm:$regclass);
> let AsmString = "";
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> let isAsCheapAsAMove = 1;
> }
> def DBG_VALUE : Instruction {
> let OutOperandList = (outs);
> let InOperandList = (ins variable_ops);
> let AsmString = "DBG_VALUE";
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> }
> def REG_SEQUENCE : Instruction {
> let OutOperandList = (outs unknown:$dst);
> let InOperandList = (ins unknown:$supersrc, variable_ops);
> let AsmString = "";
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> let isAsCheapAsAMove = 1;
> }
> def COPY : Instruction {
> let OutOperandList = (outs unknown:$dst);
> let InOperandList = (ins unknown:$src);
> let AsmString = "";
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> let isAsCheapAsAMove = 1;
> }
> def BUNDLE : Instruction {
> @@ -826,13 +826,13 @@ def LIFETIME_START : Instruction {
> let OutOperandList = (outs);
> let InOperandList = (ins i32imm:$id);
> let AsmString = "LIFETIME_START";
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> }
> def LIFETIME_END : Instruction {
> let OutOperandList = (outs);
> let InOperandList = (ins i32imm:$id);
> let AsmString = "LIFETIME_END";
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> }
> def STACKMAP : Instruction {
> let OutOperandList = (outs);
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Tue Nov 25 18:46:26 2014
> @@ -4383,7 +4383,7 @@ class BaseSIMDVectorLShiftLongBySize<bit
> }
>
> multiclass SIMDVectorLShiftLongBySizeBHS {
> - let neverHasSideEffects = 1 in {
> + let hasSideEffects = 0 in {
> def v8i8 : BaseSIMDVectorLShiftLongBySize<0, 0b00, V64,
> "shll", ".8h", ".8b", "8">;
> def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128,
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Tue Nov 25 18:46:26 2014
> @@ -789,7 +789,7 @@ def : Pat<(bswap (rotr GPR64:$Rn, (i64 3
> //===----------------------------------------------------------------------===//
> // Bitfield immediate extraction instruction.
> //===----------------------------------------------------------------------===//
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> defm EXTR : ExtractImm<"extr">;
> def : InstAlias<"ror $dst, $src, $shift",
> (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
> @@ -804,7 +804,7 @@ def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:
> //===----------------------------------------------------------------------===//
> // Other bitfield immediate instructions.
> //===----------------------------------------------------------------------===//
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
> defm SBFM : BitfieldImm<0b00, "sbfm">;
> defm UBFM : BitfieldImm<0b10, "ubfm">;
> @@ -977,9 +977,9 @@ def : InstAlias<"cneg $dst, $src, $cc",
> // PC-relative instructions.
> //===----------------------------------------------------------------------===//
> let isReMaterializable = 1 in {
> -let neverHasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
> +let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
> def ADR : ADRI<0, "adr", adrlabel, []>;
> -} // neverHasSideEffects = 1
> +} // hasSideEffects = 0
>
> def ADRP : ADRI<1, "adrp", adrplabel,
> [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
> @@ -4124,7 +4124,7 @@ def MVNIv4s_msl : SIMDModifiedImmMoveM
> // AdvSIMD indexed element
> //----------------------------------------------------------------------------
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
> defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
> }
> @@ -4678,7 +4678,7 @@ defm LD1R : SIMDLdR<0, 0b110, 0
> defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
> defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
> defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
> -let mayLoad = 1, neverHasSideEffects = 1 in {
> +let mayLoad = 1, hasSideEffects = 0 in {
> defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
> defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
> defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
> @@ -4848,7 +4848,7 @@ defm : St1LanePost128Pat<post_store, Vec
> defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
> defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
>
> -let mayStore = 1, neverHasSideEffects = 1 in {
> +let mayStore = 1, hasSideEffects = 0 in {
> defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
> defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
> defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 25 18:46:26 2014
> @@ -1813,7 +1813,7 @@ multiclass AI_str1nopc<bit isByte, strin
> /// the function. The first operand is the ID# for this instruction, the second
> /// is the index into the MachineConstantPool that this is, the third is the
> /// size in bytes of this constant pool entry.
> -let neverHasSideEffects = 1, isNotDuplicable = 1 in
> +let hasSideEffects = 0, isNotDuplicable = 1 in
> def CONSTPOOL_ENTRY :
> PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
> i32imm:$size), NoItinerary, []>;
> @@ -2057,7 +2057,7 @@ def PICSTRB : ARMPseudoInst<(outs), (ins
>
> // LEApcrel - Load a pc-relative address into a register without offending the
> // assembler.
> -let neverHasSideEffects = 1, isReMaterializable = 1 in
> +let hasSideEffects = 0, isReMaterializable = 1 in
> // The 'adr' mnemonic encodes differently if the label is before or after
> // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
> // know until then which form of the instruction will be used.
> @@ -2404,7 +2404,7 @@ defm STRB : AI_str1nopc<1, "strb", IIC_i
> BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
>
> // Special LDR for loads from non-pc-relative constpools.
> -let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
> +let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
> isReMaterializable = 1, isCodeGenOnly = 1 in
> def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
> AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
> @@ -2431,7 +2431,7 @@ def LDRSB : AI3ld<0b1101, 1, (outs GPR:$
> IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
> [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
>
> -let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
> +let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
> // Load doubleword
> def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
> LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
> @@ -2508,7 +2508,7 @@ multiclass AI2_ldridx<bit isByte, string
>
> }
>
> -let mayLoad = 1, neverHasSideEffects = 1 in {
> +let mayLoad = 1, hasSideEffects = 0 in {
> // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
> // IIC_iLoad_siu depending on whether it the offset register is shifted.
> defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
> @@ -2544,7 +2544,7 @@ multiclass AI3_ldridx<bits<4> op, string
> }
> }
>
> -let mayLoad = 1, neverHasSideEffects = 1 in {
> +let mayLoad = 1, hasSideEffects = 0 in {
> defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
> defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
> defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
> @@ -2577,10 +2577,10 @@ def LDRD_POST: AI3ldstidx<0b1101, 0, 0,
> let DecoderMethod = "DecodeAddrMode3Instruction";
> }
> } // hasExtraDefRegAllocReq = 1
> -} // mayLoad = 1, neverHasSideEffects = 1
> +} // mayLoad = 1, hasSideEffects = 0
>
> // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
> -let mayLoad = 1, neverHasSideEffects = 1 in {
> +let mayLoad = 1, hasSideEffects = 0 in {
> def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
> (ins addr_offset_none:$addr, am2offset_reg:$offset),
> IndexModePost, LdFrm, IIC_iLoad_ru,
> @@ -2699,7 +2699,7 @@ def STRH : AI3str<0b1011, (outs), (ins G
> [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
>
> // Store doubleword
> -let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
> +let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
> def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
> StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
> Requires<[IsARM, HasV5TE]> {
> @@ -2772,7 +2772,7 @@ multiclass AI2_stridx<bit isByte, string
> }
> }
>
> -let mayStore = 1, neverHasSideEffects = 1 in {
> +let mayStore = 1, hasSideEffects = 0 in {
> // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
> // IIC_iStore_siu depending on whether it the offset register is shifted.
> defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
> @@ -2864,7 +2864,7 @@ def STRH_POST : AI3ldstidx<0b1011, 0, 0,
> let DecoderMethod = "DecodeAddrMode3Instruction";
> }
>
> -let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
> +let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
> def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
> (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
> IndexModePre, StMiscFrm, IIC_iStore_d_ru,
> @@ -2894,7 +2894,7 @@ def STRD_POST: AI3ldstidx<0b1111, 0, 0,
> let Inst{3-0} = offset{3-0}; // imm3_0/Rm
> let DecoderMethod = "DecodeAddrMode3Instruction";
> }
> -} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
> +} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
>
> // STRT, STRBT, and STRHT
>
> @@ -2938,7 +2938,7 @@ def STRBT_POST
> : ARMAsmPseudo<"strbt${q} $Rt, $addr",
> (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
>
> -let mayStore = 1, neverHasSideEffects = 1 in {
> +let mayStore = 1, hasSideEffects = 0 in {
> def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
> (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
> IndexModePost, StFrm, IIC_iStore_ru,
> @@ -3103,7 +3103,7 @@ multiclass arm_ldst_mult<string asm, str
> }
> }
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
>
> let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
> defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
> @@ -3113,7 +3113,7 @@ let mayStore = 1, hasExtraSrcRegAllocReq
> defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
> IIC_iStore_mu>;
>
> -} // neverHasSideEffects
> +} // hasSideEffects
>
> // FIXME: remove when we have a way to marking a MI with these properties.
> // FIXME: Should pc be an implicit operand like PICADD, etc?
> @@ -3139,7 +3139,7 @@ defm sysSTM : arm_ldst_mult<"stm", " ^",
> // Move Instructions.
> //
>
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
> "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
> bits<4> Rd;
> @@ -3153,7 +3153,7 @@ def MOVr : AsI1<0b1101, (outs GPR:$Rd),
> }
>
> // A version for the smaller set of tail call registers.
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
> IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
> bits<4> Rd;
> @@ -3811,7 +3811,7 @@ def MLS : AMul1I<0b0000011, (outs GPR:$
> }
>
> // Extra precision multiplies with low / high results
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> let isCommutable = 1 in {
> def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
> (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
> @@ -3878,7 +3878,7 @@ def UMLALv5 : ARMPseudoExpand<(outs GPR:
> Requires<[IsARM, NoV6]>;
> }
>
> -} // neverHasSideEffects
> +} // hasSideEffects
>
> // Most significant word multiply
> def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
> @@ -4359,7 +4359,7 @@ def BCCZi64 : PseudoInst<(outs),
>
>
> // Conditional moves
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
>
> let isCommutable = 1, isSelect = 1 in
> def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
> @@ -4420,7 +4420,7 @@ def MVNCCi : ARMPseudoInst<(outs GPR:$Rd
> cmovpred:$p))]>,
> RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
>
> -} // neverHasSideEffects
> +} // hasSideEffects
>
>
> //===----------------------------------------------------------------------===//
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 25 18:46:26 2014
> @@ -665,7 +665,7 @@ class VLDQQQQWBPseudo<InstrItinClass iti
> (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
> "$addr.addr = $wb, $src = $dst">;
>
> -let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
> +let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
>
> // VLD1 : Vector Load (multiple single elements)
> class VLD1D<bits<4> op7_4, string Dt, Operand AddrMode>
> @@ -1023,7 +1023,7 @@ def VLD4q8oddPseudo_UPD : VLDQQQQWBPseu
> def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
> def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
>
> -} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
> +} // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
>
> // Classes for VLD*LN pseudo-instructions with multi-register operands.
> // These are expanded to real instructions after register allocation.
> @@ -1106,7 +1106,7 @@ def : Pat<(vector_insert (v4f32 QPR:$src
> (f32 (load addrmode6:$addr)), imm:$lane),
> (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
>
> -let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
> +let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
>
> // ...with address register writeback:
> class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
> @@ -1359,7 +1359,7 @@ def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,
> def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
> def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
>
> -} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
> +} // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
>
> // VLD1DUP : Vector Load (single element to all lanes)
> class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
> @@ -1405,7 +1405,7 @@ def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32
> def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
> (VLD1DUPq32 addrmode6:$addr)>;
>
> -let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
> +let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
> // ...with address register writeback:
> multiclass VLD1DUPWB<bits<4> op7_4, string Dt, Operand AddrMode> {
> def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
> @@ -1609,9 +1609,9 @@ def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo
> def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
> def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
>
> -} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
> +} // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
>
> -let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
> +let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
>
> // Classes for VST* pseudo-instructions with multi-register operands.
> // These are expanded to real instructions after register allocation.
> @@ -2025,7 +2025,7 @@ def VST4q8oddPseudo_UPD : VSTQQQQWBPseu
> def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
> def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
>
> -} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
> +} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
>
> // Classes for VST*LN pseudo-instructions with multi-register operands.
> // These are expanded to real instructions after register allocation.
> @@ -2129,7 +2129,7 @@ def VST1LNq8Pseudo_UPD : VST1QLNWBPseud
> def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
> def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
>
> -let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
> +let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
>
> // VST2LN : Vector Store (single 2-element structure from one lane)
> class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
> @@ -2351,7 +2351,7 @@ def VST4LNq32_UPD : VST4LNWB<0b1011, {?,
> def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
> def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
>
> -} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
> +} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
>
> // Use vld1/vst1 for unaligned f64 load / store
> def : Pat<(f64 (hword_alignedload addrmode6:$addr)),
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Nov 25 18:46:26 2014
> @@ -714,7 +714,7 @@ def tSTRspi : T1pIs<(outs), (ins tGPR:$R
> //
>
> // These require base address to be written back or one of the loaded regs.
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
>
> let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
> def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
> @@ -754,7 +754,7 @@ def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
> let Inst{7-0} = regs;
> }
>
> -} // neverHasSideEffects
> +} // hasSideEffects
>
> def : InstAlias<"ldm${p} $Rn!, $regs",
> (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
> @@ -888,7 +888,7 @@ def tADDrr : // A8.6.
> "add", "\t$Rd, $Rn, $Rm",
> [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
>
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
> "add", "\t$Rdn, $Rm", []>,
> T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
> @@ -1048,7 +1048,7 @@ def : tInstAlias <"movs $Rdn, $imm",
>
> // A7-73: MOV(2) - mov setting flag.
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
> 2, IIC_iMOVr,
> "mov", "\t$Rd, $Rm", "", []>,
> @@ -1070,7 +1070,7 @@ def tMOVSr : T1I<(outs tGPR:$Rd), (
> let Inst{5-3} = Rm;
> let Inst{2-0} = Rd;
> }
> -} // neverHasSideEffects
> +} // hasSideEffects
>
> // Multiply register
> let isCommutable = 1 in
> @@ -1248,7 +1248,7 @@ def tADR : T1I<(outs tGPR:$Rd), (ins t_a
> let DecoderMethod = "DecodeThumbAddSpecialReg";
> }
>
> -let neverHasSideEffects = 1, isReMaterializable = 1 in
> +let hasSideEffects = 0, isReMaterializable = 1 in
> def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
> 2, IIC_iALUi, []>, Sched<[WriteALU]>;
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Nov 25 18:46:26 2014
> @@ -1241,7 +1241,7 @@ def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd
> let DecoderMethod = "DecodeT2Adr";
> }
>
> -let neverHasSideEffects = 1, isReMaterializable = 1 in
> +let hasSideEffects = 0, isReMaterializable = 1 in
> def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
> 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
> let hasSideEffects = 1 in
> @@ -1272,12 +1272,12 @@ defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh",
> defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
> GPRnopc, UnOpFrag<(sextloadi8 node:$Src)>>;
>
> -let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
> +let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
> // Load doubleword
> def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
> (ins t2addrmode_imm8s4:$addr),
> IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
> -} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
> +} // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
>
> // zextload i1 -> zextload i8
> def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
> @@ -1326,7 +1326,7 @@ def : T2Pat<(extloadi16 (ARMWrapper tcon
>
> // Indexed loads
>
> -let mayLoad = 1, neverHasSideEffects = 1 in {
> +let mayLoad = 1, hasSideEffects = 0 in {
> def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
> (ins t2addrmode_imm8_pre:$addr),
> AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
> @@ -1378,7 +1378,7 @@ def t2LDRSH_POST : T2Ipostldst<1, 0b01,
> (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
> AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
> "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
> -} // mayLoad = 1, neverHasSideEffects = 1
> +} // mayLoad = 1, hasSideEffects = 0
>
> // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
> // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
> @@ -1443,14 +1443,14 @@ defm t2STRH:T2I_st<0b01,"strh", IIC_iSto
> rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
>
> // Store doubleword
> -let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
> +let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in
> def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
> (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
> IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
>
> // Indexed stores
>
> -let mayStore = 1, neverHasSideEffects = 1 in {
> +let mayStore = 1, hasSideEffects = 0 in {
> def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
> (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr),
> AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
> @@ -1468,7 +1468,7 @@ def t2STRB_PRE : T2Ipreldst<0, 0b00, 0,
> AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
> "strb", "\t$Rt, $addr!",
> "$addr.base = $Rn_wb, at earlyclobber $Rn_wb", []>;
> -} // mayStore = 1, neverHasSideEffects = 1
> +} // mayStore = 1, hasSideEffects = 0
>
> def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
> (ins GPRnopc:$Rt, addr_offset_none:$Rn,
> @@ -1763,7 +1763,7 @@ multiclass thumb2_ld_mult<string asm, In
> }
> }
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
>
> let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
> defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
> @@ -1848,14 +1848,14 @@ multiclass thumb2_st_mult<string asm, In
> let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
> defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
>
> -} // neverHasSideEffects
> +} // hasSideEffects
>
>
> //===----------------------------------------------------------------------===//
> // Move Instructions.
> //
>
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
> "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
> let Inst{31-27} = 0b11101;
> @@ -2572,7 +2572,7 @@ def t2MLS: T2FourReg<
> }
>
> // Extra precision multiplies with low / high results
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> let isCommutable = 1 in {
> def t2SMULL : T2MulLong<0b000, 0b0000,
> (outs rGPR:$RdLo, rGPR:$RdHi),
> @@ -2603,7 +2603,7 @@ def t2UMAAL : T2MulLong<0b110, 0b0110,
> (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
> "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
> Requires<[IsThumb2, HasThumb2DSP]>;
> -} // neverHasSideEffects
> +} // hasSideEffects
>
> // Rounding variants of the below included for disassembly only
>
> @@ -3150,7 +3150,7 @@ defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
> BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
>
> // Conditional moves
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
>
> let isCommutable = 1, isSelect = 1 in
> def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
> @@ -3213,7 +3213,7 @@ def t2MOVCCi32imm
> RegConstraint<"$false = $dst">;
> } // isCodeGenOnly = 1
>
> -} // neverHasSideEffects
> +} // hasSideEffects
>
> //===----------------------------------------------------------------------===//
> // Atomic operations intrinsics
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Nov 25 18:46:26 2014
> @@ -194,7 +194,7 @@ multiclass vfp_ldst_mult<string asm, bit
> }
> }
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
>
> let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
> defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
> @@ -202,7 +202,7 @@ defm VLDM : vfp_ldst_mult<"vldm", 1, IIC
> let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
> defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>;
>
> -} // neverHasSideEffects
> +} // hasSideEffects
>
> def : MnemonicAlias<"vldm", "vldmia">;
> def : MnemonicAlias<"vstm", "vstmia">;
> @@ -769,7 +769,7 @@ def VSQRTS : ASuI<0b11101, 0b11, 0b0001,
> IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
> [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
> (outs DPR:$Dd), (ins DPR:$Dm),
> IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
> @@ -777,7 +777,7 @@ def VMOVD : ADuI<0b11101, 0b11, 0b0000,
> def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
> (outs SPR:$Sd), (ins SPR:$Sm),
> IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
> -} // neverHasSideEffects
> +} // hasSideEffects
>
> //===----------------------------------------------------------------------===//
> // FP <-> GPR Copies. Int <-> FP Conversions.
> @@ -827,7 +827,7 @@ def VMOVSR : AVConv4I<0b11100000, 0b1010
> let D = VFPNeonDomain;
> }
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def VMOVRRD : AVConv3I<0b11000101, 0b1011,
> (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
> IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
> @@ -876,7 +876,7 @@ def VMOVRRS : AVConv3I<0b11000101, 0b10
> let D = VFPNeonDomain;
> let DecoderMethod = "DecodeVMOVRRS";
> }
> -} // neverHasSideEffects
> +} // hasSideEffects
>
> // FMDHR: GPR -> SPR
> // FMDLR: GPR -> SPR
> @@ -907,7 +907,7 @@ def VMOVDRR : AVConv5I<0b11000100, 0b101
> let isRegSequence = 1;
> }
>
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def VMOVSRR : AVConv5I<0b11000100, 0b1010,
> (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
> IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
> @@ -1543,7 +1543,7 @@ def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg
> // FP Conditional moves.
> //
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
> IIC_fpUNA64,
> [(set (f64 DPR:$Dd),
> @@ -1555,7 +1555,7 @@ def VMOVScc : PseudoInst<(outs SPR:$Sd)
> [(set (f32 SPR:$Sd),
> (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
> RegConstraint<"$Sn = $Sd">, Requires<[HasVFP2]>;
> -} // neverHasSideEffects
> +} // hasSideEffects
>
> //===----------------------------------------------------------------------===//
> // Move from VFP System Register to ARM core register.
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Tue Nov 25 18:46:26 2014
> @@ -343,7 +343,7 @@ class T_Combine : ALU32_rr<(outs DoubleR
> multiclass Combine_base {
> let BaseOpcode = "combine" in {
> def NAME : T_Combine;
> - let neverHasSideEffects = 1, isPredicated = 1 in {
> + let hasSideEffects = 0, isPredicated = 1 in {
> defm Pt : ALU32_Pred<"combine", DoubleRegs, 0>;
> defm NotPt : ALU32_Pred<"combine", DoubleRegs, 1>;
> }
> @@ -394,7 +394,7 @@ multiclass ALU32ri_base<string mnemonic,
> (s16ExtPred:$src2)))]>;
>
> let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
> - neverHasSideEffects = 1, isPredicated = 1 in {
> + hasSideEffects = 0, isPredicated = 1 in {
> defm Pt : ALU32ri_Pred<mnemonic, 0>;
> defm NotPt : ALU32ri_Pred<mnemonic, 1>;
> }
> @@ -457,7 +457,7 @@ multiclass TFR_Pred<bit PredNot> {
> }
> }
>
> -let InputType = "reg", neverHasSideEffects = 1 in
> +let InputType = "reg", hasSideEffects = 0 in
> multiclass TFR_base<string CextOp> {
> let CextOpcode = CextOp, BaseOpcode = CextOp in {
> let isPredicable = 1 in
> @@ -503,7 +503,7 @@ multiclass TFR64_Pred<bit PredNot> {
> }
> }
>
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> multiclass TFR64_base<string BaseName> {
> let BaseOpcode = BaseName in {
> let isPredicable = 1 in
> @@ -554,7 +554,7 @@ multiclass TFRI_base<string CextOp> {
> "$dst = #$src1",
> [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
>
> - let opExtendable = 2, opExtentBits = 12, neverHasSideEffects = 1,
> + let opExtendable = 2, opExtentBits = 12, hasSideEffects = 0,
> isPredicated = 1 in {
> defm Pt : TFRI_Pred<0>;
> defm NotPt : TFRI_Pred<1>;
> @@ -567,7 +567,7 @@ defm TFR : TFR_base<"TFR">, ImmRegRel, P
> defm TFR64 : TFR64_base<"TFR64">, PredNewRel;
>
> // Transfer control register.
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
> "$dst = $src1",
> []>;
> @@ -580,7 +580,7 @@ def TFCR : CRInst<(outs CRRegs:$dst), (i
> // ALU32/PERM +
> //===----------------------------------------------------------------------===//
>
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
> (ins s8Imm:$src1, s8Imm:$src2),
> "$dst = combine(#$src1, #$src2)",
> @@ -914,7 +914,7 @@ def AND_pp : SInst<(outs PredRegs:$dst),
> [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
> (i1 PredRegs:$src2)))]>;
>
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
> PredRegs:$src2),
> "$dst = and($src1, !$src2)",
> @@ -1088,7 +1088,7 @@ multiclass JMPR_base<string BaseOp> {
> }
> }
>
> -let isTerminator = 1, neverHasSideEffects = 1 in {
> +let isTerminator = 1, hasSideEffects = 0 in {
> let isBranch = 1 in
> defm JMP : JMP_base<"JMP">, PredNewRel;
>
> @@ -1106,7 +1106,7 @@ def : Pat <(brcond (i1 PredRegs:$src1),
> (JMP_t (i1 PredRegs:$src1), bb:$offset)>;
>
> // A return through builtin_eh_return.
> -let isReturn = 1, isTerminator = 1, isBarrier = 1, neverHasSideEffects = 1,
> +let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
> isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
> def EH_RETURN_JMPR : T_JMPr;
>
> @@ -1146,7 +1146,7 @@ multiclass LD_MEMri_Pred<string mnemonic
> }
> }
>
> -let isExtendable = 1, neverHasSideEffects = 1 in
> +let isExtendable = 1, hasSideEffects = 0 in
> multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
> bits<5> ImmBits, bits<5> PredImmBits> {
>
> @@ -1222,7 +1222,7 @@ multiclass LD_Idxd_Pred<string mnemonic,
> }
> }
>
> -let isExtendable = 1, neverHasSideEffects = 1 in
> +let isExtendable = 1, hasSideEffects = 0 in
> multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
> Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
> bits<5> PredImmBits> {
> @@ -1327,7 +1327,7 @@ multiclass LD_PostInc<string mnemonic, s
> }
> }
>
> -let hasCtrlDep = 1, neverHasSideEffects = 1, addrMode = PostInc in {
> +let hasCtrlDep = 1, hasSideEffects = 0, addrMode = PostInc in {
> defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
> PredNewRel;
> defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
> @@ -1371,14 +1371,14 @@ def : Pat < (i32 (zextloadi1 (add IntReg
>
> // Load predicate.
> let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
> -isPseudo = 1, Defs = [R10,R11,D5], neverHasSideEffects = 1 in
> +isPseudo = 1, Defs = [R10,R11,D5], hasSideEffects = 0 in
> def LDriw_pred : LDInst2<(outs PredRegs:$dst),
> (ins MEMri:$addr),
> "Error; should not emit",
> []>;
>
> // Deallocate stack frame.
> -let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
> +let Defs = [R29, R30, R31], Uses = [R29], hasSideEffects = 0 in {
> def DEALLOCFRAME : LDInst2<(outs), (ins),
> "deallocframe",
> []>;
> @@ -1637,7 +1637,7 @@ multiclass ST_PostInc_Pred<string mnemon
> }
> }
>
> -let hasCtrlDep = 1, isNVStorable = 1, neverHasSideEffects = 1 in
> +let hasCtrlDep = 1, isNVStorable = 1, hasSideEffects = 0 in
> multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
> Operand ImmOp> {
>
> @@ -1701,7 +1701,7 @@ multiclass ST_MEMri_Pred<string mnemonic
> }
> }
>
> -let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
> +let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
> multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
> bits<5> ImmBits, bits<5> PredImmBits> {
>
> @@ -1773,7 +1773,7 @@ multiclass ST_Idxd_Pred<string mnemonic,
> }
> }
>
> -let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
> +let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
> multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
> Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
> bits<5> PredImmBits> {
> @@ -1837,14 +1837,14 @@ def : Pat<(store (i64 DoubleRegs:$src1),
>
> // Store word.
> // Store predicate.
> -let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
> +let Defs = [R10,R11,D5], hasSideEffects = 0 in
> def STriw_pred : STInst2<(outs),
> (ins MEMri:$addr, PredRegs:$src1),
> "Error; should not emit",
> []>;
>
> // Allocate stack frame.
> -let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
> +let Defs = [R29, R30], Uses = [R31, R30], hasSideEffects = 0 in {
> def ALLOCFRAME : STInst2<(outs),
> (ins i32imm:$amt),
> "allocframe(#$amt)",
> @@ -1918,7 +1918,7 @@ def : Pat <(xor (i32 IntRegs:$src1), -21
> (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
>
> // Predicate transfer.
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
> "$dst = $src1 /* Should almost never emit this. */",
> []>;
> @@ -2093,19 +2093,19 @@ def TFR_FI : ALU32_ri<(outs IntRegs:$dst
> //
> // CR - Type.
> //
> -let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
> +let hasSideEffects = 0, Defs = [SA0, LC0] in {
> def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
> "loop0($offset, #$src2)",
> []>;
> }
>
> -let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
> +let hasSideEffects = 0, Defs = [SA0, LC0] in {
> def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
> "loop0($offset, $src2)",
> []>;
> }
>
> -let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
> +let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
> Defs = [PC, LC0], Uses = [SA0, LC0] in {
> def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
> ":endloop0",
> @@ -2122,44 +2122,44 @@ def HexagonCONST32 : SDNode<"HexagonISD:
> def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
>
> // HI/LO Instructions
> -let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
> +let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
> def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
> "$dst.l = #LO($global)",
> []>;
>
> -let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
> +let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
> def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
> "$dst.h = #HI($global)",
> []>;
>
> -let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
> +let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
> def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
> "$dst.l = #LO($imm_value)",
> []>;
>
>
> -let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
> +let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
> def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
> "$dst.h = #HI($imm_value)",
> []>;
>
> -let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
> +let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
> def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
> "$dst.l = #LO($jt)",
> []>;
>
> -let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
> +let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
> def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
> "$dst.h = #HI($jt)",
> []>;
>
>
> -let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
> +let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
> def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
> "$dst.l = #LO($label)",
> []>;
>
> -let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
> +let isReMaterializable = 1, isMoveImm = 1 , hasSideEffects = 0 in
> def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
> "$dst.h = #HI($label)",
> []>;
> @@ -2257,7 +2257,7 @@ let Defs = [R29, R30, R31], Uses = [R29]
> [(callseq_end timm:$amt1, timm:$amt2)]>;
> }
> // Call subroutine.
> -let isCall = 1, neverHasSideEffects = 1,
> +let isCall = 1, hasSideEffects = 0,
> Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
> R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
> def CALL : JInst<(outs), (ins calltarget:$dst),
> @@ -2265,7 +2265,7 @@ let isCall = 1, neverHasSideEffects = 1,
> }
>
> // Call subroutine from register.
> -let isCall = 1, neverHasSideEffects = 1,
> +let isCall = 1, hasSideEffects = 0,
> Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
> R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
> def CALLR : JRInst<(outs), (ins IntRegs:$dst),
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td Tue Nov 25 18:46:26 2014
> @@ -21,7 +21,7 @@ def callv3nr : SDNode<"HexagonISD::CALLv
> // J +
> //===----------------------------------------------------------------------===//
> // Call subroutine.
> -let isCall = 1, neverHasSideEffects = 1,
> +let isCall = 1, hasSideEffects = 0,
> Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
> P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
> def CALLv3 : JInst<(outs), (ins calltarget:$dst),
> @@ -37,7 +37,7 @@ let isCall = 1, neverHasSideEffects = 1,
> // JR +
> //===----------------------------------------------------------------------===//
> // Call subroutine from register.
> -let isCall = 1, neverHasSideEffects = 1,
> +let isCall = 1, hasSideEffects = 0,
> Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
> P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
> def CALLRv3 : JRInst<(outs), (ins IntRegs:$dst),
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Tue Nov 25 18:46:26 2014
> @@ -11,7 +11,7 @@
> //
> //===----------------------------------------------------------------------===//
>
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> class T_Immext<dag ins> :
> EXTENDERInst<(outs), ins, "immext(#$imm)", []>,
> Requires<[HasV4T]>;
> @@ -96,7 +96,7 @@ def NumUsesBelowThresCONST32 : PatFrag<(
> // ALU32 +
> //===----------------------------------------------------------------------===//
> // Generate frame index addresses.
> -let neverHasSideEffects = 1, isReMaterializable = 1,
> +let hasSideEffects = 0, isReMaterializable = 1,
> isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
> def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
> (ins IntRegs:$src1, s32Imm:$offset),
> @@ -165,7 +165,7 @@ def V4_A4_rcmpneq : ALU32_ri<(outs IntRe
> // Combine
> // Rdd=combine(Rs, #s8)
> let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
> - neverHasSideEffects = 1, validSubTargets = HasV4SubT in
> + hasSideEffects = 0, validSubTargets = HasV4SubT in
> def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
> (ins IntRegs:$src1, s8Ext:$src2),
> "$dst = combine($src1, #$src2)",
> @@ -174,7 +174,7 @@ def COMBINE_rI_V4 : ALU32_ri<(outs Doubl
>
> // Rdd=combine(#s8, Rs)
> let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
> - neverHasSideEffects = 1, validSubTargets = HasV4SubT in
> + hasSideEffects = 0, validSubTargets = HasV4SubT in
> def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
> (ins s8Ext:$src1, IntRegs:$src2),
> "$dst = combine(#$src1, $src2)",
> @@ -195,7 +195,7 @@ def : Pat <(HexagonWrapperCombineIR_V4 s
> Requires<[HasV4T]>;
>
> let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
> - neverHasSideEffects = 1, validSubTargets = HasV4SubT in
> + hasSideEffects = 0, validSubTargets = HasV4SubT in
> def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
> (ins s8Imm:$src1, u6Ext:$src2),
> "$dst = combine(#$src1, #$src2)",
> @@ -212,7 +212,7 @@ def COMBINE_iI_V4 : ALU32_ii<(outs Doubl
> //===----------------------------------------------------------------------===//
> // Template class for load instructions with Absolute set addressing mode.
> //===----------------------------------------------------------------------===//
> -let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
> +let isExtended = 1, opExtendable = 2, hasSideEffects = 0,
> validSubTargets = HasV4SubT, addrMode = AbsoluteSet in
> class T_LD_abs_set<string mnemonic, RegisterClass RC>:
> LDInst2<(outs RC:$dst1, IntRegs:$dst2),
> @@ -249,7 +249,7 @@ multiclass ld_idxd_shl_pred<string mnemo
> }
> }
>
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
> let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
> let isPredicable = 1 in
> @@ -561,7 +561,7 @@ multiclass ST_Idxd_shl_nv<string mnemoni
> }
> }
>
> -let addrMode = BaseRegOffset, neverHasSideEffects = 1,
> +let addrMode = BaseRegOffset, hasSideEffects = 0,
> validSubTargets = HasV4SubT in {
> let accessSize = ByteAccess in
> defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>,
> @@ -692,7 +692,7 @@ multiclass ST_Imm_Pred<string mnemonic,
> }
> }
>
> -let isExtendable = 1, isExtentSigned = 1, neverHasSideEffects = 1 in
> +let isExtendable = 1, isExtentSigned = 1, hasSideEffects = 0 in
> multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
> let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
> let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
> @@ -782,7 +782,7 @@ def : Pat <(truncstorei16 s8ExtPred:$src
> // TODO: Needs to be implemented.
>
> // Store predicate:
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def STriw_pred_V4 : STInst2<(outs),
> (ins MEMri:$addr, PredRegs:$src1),
> "Error; should not emit",
> @@ -831,7 +831,7 @@ multiclass ST_Idxd_Pred_nv<string mnemon
> }
> }
>
> -let mayStore = 1, isNVStore = 1, neverHasSideEffects = 1, isExtendable = 1 in
> +let mayStore = 1, isNVStore = 1, hasSideEffects = 0, isExtendable = 1 in
> multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
> Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
> bits<5> PredImmBits> {
> @@ -889,7 +889,7 @@ multiclass ST_MEMri_Pred_nv<string mnemo
> }
> }
>
> -let mayStore = 1, isNVStore = 1, isExtendable = 1, neverHasSideEffects = 1 in
> +let mayStore = 1, isNVStore = 1, isExtendable = 1, hasSideEffects = 0 in
> multiclass ST_MEMri_nv<string mnemonic, string CextOp, RegisterClass RC,
> bits<5> ImmBits, bits<5> PredImmBits> {
>
> @@ -903,7 +903,7 @@ multiclass ST_MEMri_nv<string mnemonic,
> Requires<[HasV4T]>;
>
> let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
> - neverHasSideEffects = 1, isPredicated = 1 in {
> + hasSideEffects = 0, isPredicated = 1 in {
> defm Pt : ST_MEMri_Pred_nv<mnemonic, RC, 0>;
> defm NotPt : ST_MEMri_Pred_nv<mnemonic, RC, 1>;
> }
> @@ -949,7 +949,7 @@ multiclass ST_PostInc_Pred_nv<string mne
> }
> }
>
> -let hasCtrlDep = 1, isNVStore = 1, neverHasSideEffects = 1 in
> +let hasCtrlDep = 1, isNVStore = 1, hasSideEffects = 0 in
> multiclass ST_PostInc_nv<string mnemonic, string BaseOp, RegisterClass RC,
> Operand ImmOp> {
>
> @@ -1064,7 +1064,7 @@ multiclass NVJrr_base<string mnemonic, s
> // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
>
> let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
> - Defs = [PC], neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
> + Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT in {
> defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
> defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
> defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
> @@ -1124,7 +1124,7 @@ multiclass NVJri_base<string mnemonic, s
> // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
>
> let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
> - Defs = [PC], neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
> + Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT in {
> defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
> defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
> defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
> @@ -1182,7 +1182,7 @@ multiclass NVJ_ConstImm_base<string mnem
> // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
>
> let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
> - Defs = [PC], neverHasSideEffects = 1 in {
> + Defs = [PC], hasSideEffects = 0 in {
> defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
> defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
> defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
> @@ -2579,7 +2579,7 @@ def NTSTBIT_ri : SInst<(outs PredRegs:$d
> //Deallocate frame and return.
> // dealloc_return
> let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
> - Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1 in {
> + Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in {
> let validSubTargets = HasV4SubT in
> def DEALLOC_RET_V4 : LD0Inst<(outs), (ins),
> "dealloc_return",
> @@ -2621,7 +2621,7 @@ let isCall = 1, isBarrier = 1,
>
> // if (Ps) dealloc_return
> let isReturn = 1, isTerminator = 1,
> - Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
> + Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
> isPredicated = 1 in {
> let validSubTargets = HasV4SubT in
> def DEALLOC_RET_cPt_V4 : LD0Inst<(outs),
> @@ -2633,7 +2633,7 @@ let validSubTargets = HasV4SubT in
>
> // if (!Ps) dealloc_return
> let isReturn = 1, isTerminator = 1,
> - Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
> + Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
> isPredicated = 1, isPredicatedFalse = 1 in {
> let validSubTargets = HasV4SubT in
> def DEALLOC_RET_cNotPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
> @@ -2644,7 +2644,7 @@ let validSubTargets = HasV4SubT in
>
> // if (Ps.new) dealloc_return:nt
> let isReturn = 1, isTerminator = 1,
> - Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
> + Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
> isPredicated = 1 in {
> let validSubTargets = HasV4SubT in
> def DEALLOC_RET_cdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
> @@ -2655,7 +2655,7 @@ let validSubTargets = HasV4SubT in
>
> // if (!Ps.new) dealloc_return:nt
> let isReturn = 1, isTerminator = 1,
> - Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
> + Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
> isPredicated = 1, isPredicatedFalse = 1 in {
> let validSubTargets = HasV4SubT in
> def DEALLOC_RET_cNotdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
> @@ -2666,7 +2666,7 @@ let validSubTargets = HasV4SubT in
>
> // if (Ps.new) dealloc_return:t
> let isReturn = 1, isTerminator = 1,
> - Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
> + Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
> isPredicated = 1 in {
> let validSubTargets = HasV4SubT in
> def DEALLOC_RET_cdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
> @@ -2677,7 +2677,7 @@ let validSubTargets = HasV4SubT in
>
> // if (!Ps.new) dealloc_return:nt
> let isReturn = 1, isTerminator = 1,
> - Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
> + Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
> isPredicated = 1, isPredicatedFalse = 1 in {
> let validSubTargets = HasV4SubT in
> def DEALLOC_RET_cNotdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
> @@ -2708,7 +2708,7 @@ multiclass ST_Abs_Pred<string mnemonic,
> }
> }
>
> -let isNVStorable = 1, isExtended = 1, neverHasSideEffects = 1 in
> +let isNVStorable = 1, isExtended = 1, hasSideEffects = 0 in
> multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC> {
> let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
> let opExtendable = 0, isPredicable = 1 in
> @@ -2744,7 +2744,7 @@ multiclass ST_Abs_Pred_nv<string mnemoni
> }
> }
>
> -let mayStore = 1, isNVStore = 1, isExtended = 1, neverHasSideEffects = 1 in
> +let mayStore = 1, isNVStore = 1, isExtended = 1, hasSideEffects = 0 in
> multiclass ST_Abs_nv<string mnemonic, string CextOp, RegisterClass RC> {
> let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
> let opExtendable = 0, isPredicable = 1 in
> @@ -2835,7 +2835,7 @@ multiclass ST_GP_nv<string mnemonic, str
> }
> }
>
> -let validSubTargets = HasV4SubT, neverHasSideEffects = 1 in {
> +let validSubTargets = HasV4SubT, hasSideEffects = 0 in {
> let isNVStorable = 0 in
> defm STd_GP : ST_GP <"memd", "STd_GP", DoubleRegs>, PredNewRel;
>
> @@ -2918,7 +2918,7 @@ multiclass LD_Abs_Pred<string mnemonic,
> }
> }
>
> -let isExtended = 1, neverHasSideEffects = 1 in
> +let isExtended = 1, hasSideEffects = 0 in
> multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC> {
> let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
> let opExtendable = 1, isPredicable = 1 in
> @@ -2973,7 +2973,7 @@ def : Pat<(i32 (zextloadi16 (HexagonCONS
> // Rx=mem[bhwd](##global)
> // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
> //===----------------------------------------------------------------------===//
> -let neverHasSideEffects = 1, validSubTargets = HasV4SubT in
> +let hasSideEffects = 0, validSubTargets = HasV4SubT in
> multiclass LD_GP<string mnemonic, string BaseOp, RegisterClass RC> {
> let BaseOpcode = BaseOp in {
> let isPredicable = 1 in
> @@ -3083,7 +3083,7 @@ def : Pat<(HexagonCONST32_GP tblockaddre
> Requires<[HasV4T]>;
>
> let isExtended = 1, opExtendable = 2, AddedComplexity=50,
> -neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
> +hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
> def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
> (ins PredRegs:$src1, s16Ext:$src2),
> "if($src1) $dst = #$src2",
> @@ -3091,7 +3091,7 @@ def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs
> Requires<[HasV4T]>;
>
> let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
> -neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
> +hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
> def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
> (ins PredRegs:$src1, s16Ext:$src2),
> "if(!$src1) $dst = #$src2",
> @@ -3099,7 +3099,7 @@ def TFRI_cNotPt_V4 : ALU32_ri<(outs IntR
> Requires<[HasV4T]>;
>
> let isExtended = 1, opExtendable = 2, AddedComplexity=50,
> -neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
> +hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
> def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
> (ins PredRegs:$src1, s16Ext:$src2),
> "if($src1.new) $dst = #$src2",
> @@ -3107,7 +3107,7 @@ def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRe
> Requires<[HasV4T]>;
>
> let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
> -neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
> +hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
> def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
> (ins PredRegs:$src1, s16Ext:$src2),
> "if(!$src1.new) $dst = #$src2",
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td Tue Nov 25 18:46:26 2014
> @@ -37,7 +37,7 @@ def TFRI_f : ALU32_ri<(outs IntRegs:$dst
> Requires<[HasV5T]>;
>
> let isExtended = 1, opExtendable = 2, isPredicated = 1,
> -neverHasSideEffects = 1, validSubTargets = HasV5SubT in
> +hasSideEffects = 0, validSubTargets = HasV5SubT in
> def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
> (ins PredRegs:$src1, f32Ext:$src2),
> "if ($src1) $dst = #$src2",
> @@ -45,7 +45,7 @@ def TFRI_cPt_f : ALU32_ri<(outs IntRegs:
> Requires<[HasV5T]>;
>
> let isExtended = 1, opExtendable = 2, isPredicated = 1, isPredicatedFalse = 1,
> -neverHasSideEffects = 1, validSubTargets = HasV5SubT in
> +hasSideEffects = 0, validSubTargets = HasV5SubT in
> def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst),
> (ins PredRegs:$src1, f32Ext:$src2),
> "if (!$src1) $dst =#$src2",
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td Tue Nov 25 18:46:26 2014
> @@ -1851,7 +1851,7 @@ class T_RI_pat <InstHexagon MI, Intrinsi
> //
> // LDInst classes.
> //
> -let mayLoad = 1, neverHasSideEffects = 1 in
> +let mayLoad = 1, hasSideEffects = 0 in
> class di_LDInstPI_diu4<string opc, Intrinsic IntID>
> : LDInstPI<(outs IntRegs:$dst, DoubleRegs:$dst2),
> (ins IntRegs:$src1, IntRegs:$src2, CRRegs:$src3, s4Imm:$offset),
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td Tue Nov 25 18:46:26 2014
> @@ -153,7 +153,7 @@ let usesCustomInserter = 1 in {
> }
> }
>
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def NOP : Pseudo<(outs), (ins), "nop", []>;
>
> //===----------------------------------------------------------------------===//
> @@ -224,7 +224,7 @@ let isCall = 1 in
> //===----------------------------------------------------------------------===//
> // Miscellaneous Instructions...
> //
> -let Defs = [SP], Uses = [SP], neverHasSideEffects=1 in {
> +let Defs = [SP], Uses = [SP], hasSideEffects=0 in {
> let mayLoad = 1 in
> def POP16r : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
> (outs GR16:$reg), (ins), "pop.w\t$reg", []>;
> @@ -238,7 +238,7 @@ def PUSH16r : II16r<0x0,
> // Move Instructions
>
> // FIXME: Provide proper encoding!
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def MOV8rr : I8rr<0x0,
> (outs GR8:$dst), (ins GR8:$src),
> "mov.b\t{$src, $dst}",
>
> Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td Tue Nov 25 18:46:26 2014
> @@ -502,7 +502,7 @@ class ArithLogic16Defs<bit isCom=0> {
> bits<5> shamt = 0;
> bit isCommutable = isCom;
> bit isReMaterializable = 1;
> - bit neverHasSideEffects = 1;
> + bit hasSideEffects = 0;
> }
>
> class branch16 {
> @@ -879,7 +879,7 @@ def MoveR3216: FI8_MOVR3216_ins<"move",
> //
> def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
> let Uses = [HI0];
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> }
>
> //
> @@ -889,7 +889,7 @@ def Mfhi16: FRR16_M_ins<0b10000, "mfhi",
> //
> def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
> let Uses = [LO0];
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> }
>
> //
> @@ -897,13 +897,13 @@ def Mflo16: FRR16_M_ins<0b10010, "mflo",
> //
> def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
> let isCommutable = 1;
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> let Defs = [HI0, LO0];
> }
>
> def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
> let isCommutable = 1;
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> let Defs = [HI0, LO0];
> }
>
> @@ -914,7 +914,7 @@ def MultuRxRy16: FMULT16_ins<"multu", II
> //
> def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
> let isCommutable = 1;
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> let Defs = [HI0, LO0];
> }
>
> @@ -925,7 +925,7 @@ def MultRxRyRz16: FMULT16_LO_ins<"mult",
> //
> def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
> let isCommutable = 1;
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> let Defs = [HI0, LO0];
> }
>
> @@ -1910,7 +1910,7 @@ def cpinst_operand : Operand<i32> {
> // is the index into the MachineConstantPool that this is, the third is the
> // size in bytes of this constant pool entry.
> //
> -let neverHasSideEffects = 1, isNotDuplicable = 1 in
> +let hasSideEffects = 0, isNotDuplicable = 1 in
> def CONSTPOOL_ENTRY :
> MipsPseudo16<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
> i32imm:$size), "foo", []>;
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Nov 25 18:46:26 2014
> @@ -316,7 +316,7 @@ class IsAsCheapAsAMove {
> }
>
> class NeverHasSideEffects {
> - bit neverHasSideEffects = 1;
> + bit hasSideEffects = 0;
> }
>
> //===----------------------------------------------------------------------===//
> @@ -632,7 +632,7 @@ class shift_rotate_reg<string opstr, Reg
> class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
> InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
> [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> let isReMaterializable = 1;
> }
>
> @@ -876,7 +876,7 @@ class Mult<string opstr, InstrItinClass
> itin, FrmR, opstr> {
> let isCommutable = 1;
> let Defs = DefRegs;
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> }
>
> // Pseudo multiply/divide instruction with explicit accumulator register
> @@ -922,7 +922,7 @@ class MoveFromLOHI<string opstr, Registe
> InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
> FrmR, opstr> {
> let Uses = [UseReg];
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> }
>
> class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
> @@ -934,7 +934,7 @@ class MoveToLOHI<string opstr, RegisterO
> InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
> FrmR, opstr> {
> let Defs = DefRegs;
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> }
>
> class EffectiveAddress<string opstr, RegisterOperand RO> :
> @@ -964,7 +964,7 @@ class SignExtInReg<string opstr, ValueTy
> class SubwordSwap<string opstr, RegisterOperand RO>:
> InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
> NoItinerary, FrmR, opstr> {
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> }
>
> // Read Hardware
>
> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td Tue Nov 25 18:46:26 2014
> @@ -296,7 +296,7 @@ multiclass F2<string OpcStr, SDNode OpNo
> // General Type Conversion
> //-----------------------------------
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> // Generate a cvt to the given type from all possible types.
> // Each instance takes a CvtMode immediate that defines the conversion mode to
> // use. It can be CvtNONE to omit a conversion mode.
> @@ -2094,7 +2094,7 @@ multiclass LD<NVPTXRegClass regclass> {
> "$fromWidth \t$dst, [$addr+$offset];"), []>;
> }
>
> -let mayLoad=1, neverHasSideEffects=1 in {
> +let mayLoad=1, hasSideEffects=0 in {
> defm LD_i8 : LD<Int16Regs>;
> defm LD_i16 : LD<Int16Regs>;
> defm LD_i32 : LD<Int32Regs>;
> @@ -2136,7 +2136,7 @@ multiclass ST<NVPTXRegClass regclass> {
> " \t[$addr+$offset], $src;"), []>;
> }
>
> -let mayStore=1, neverHasSideEffects=1 in {
> +let mayStore=1, hasSideEffects=0 in {
> defm ST_i8 : ST<Int16Regs>;
> defm ST_i16 : ST<Int16Regs>;
> defm ST_i32 : ST<Int32Regs>;
> @@ -2220,7 +2220,7 @@ multiclass LD_VEC<NVPTXRegClass regclass
> "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),
> []>;
> }
> -let mayLoad=1, neverHasSideEffects=1 in {
> +let mayLoad=1, hasSideEffects=0 in {
> defm LDV_i8 : LD_VEC<Int16Regs>;
> defm LDV_i16 : LD_VEC<Int16Regs>;
> defm LDV_i32 : LD_VEC<Int32Regs>;
> @@ -2303,7 +2303,7 @@ multiclass ST_VEC<NVPTXRegClass regclass
> "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"),
> []>;
> }
> -let mayStore=1, neverHasSideEffects=1 in {
> +let mayStore=1, hasSideEffects=0 in {
> defm STV_i8 : ST_VEC<Int16Regs>;
> defm STV_i16 : ST_VEC<Int16Regs>;
> defm STV_i32 : ST_VEC<Int32Regs>;
>
> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXVector.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXVector.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/NVPTX/NVPTXVector.td (original)
> +++ llvm/trunk/lib/Target/NVPTX/NVPTXVector.td Tue Nov 25 18:46:26 2014
> @@ -661,7 +661,7 @@ class ShuffleAsmStr4<string type>
> string s = !strconcat(t6, ShuffleOneLine<"4", "3", type>.s);
> }
>
> -let neverHasSideEffects=1, VecInstType=isVecShuffle.Value in {
> +let hasSideEffects=0, VecInstType=isVecShuffle.Value in {
> def VecShuffle_v4f32 : NVPTXVecInst<(outs V4F32Regs:$dst),
> (ins V4F32Regs:$src1, V4F32Regs:$src2,
> i8imm:$c0, i8imm:$c1, i8imm:$c2, i8imm:$c3),
> @@ -847,7 +847,7 @@ class Vec_Move<string asmstr, NVPTXRegCl
> !strconcat(asmstr, "\t${dst:vecfull}, ${src:vecfull};"),
> [], sop>;
>
> -let isAsCheapAsAMove=1, neverHasSideEffects=1, IsSimpleMove=1,
> +let isAsCheapAsAMove=1, hasSideEffects=0, IsSimpleMove=1,
> VecInstType=isVecOther.Value in {
> def V4f32Mov : Vec_Move<"mov.v4.f32", V4F32Regs, FMOV32rr>;
> def V2f32Mov : Vec_Move<"mov.v2.f32", V2F32Regs, FMOV32rr>;
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Tue Nov 25 18:46:26 2014
> @@ -282,7 +282,7 @@ def : Pat<(PPCtc_return CTRRC8:$dst, imm
>
> // 64-bit CR instructions
> let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
> "mtocrf $FXM, $ST", IIC_BrMCRX>,
> PPC970_DGroup_First, PPC970_Unit_CRU;
> @@ -299,7 +299,7 @@ def MFOCRF8: XFXForm_5a<31, 19, (outs g8
> def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
> "mfcr $rT", IIC_SprMFCR>,
> PPC970_MicroCode, PPC970_Unit_CRU;
> -} // neverHasSideEffects = 1
> +} // hasSideEffects = 0
>
> let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
> let Defs = [CTR8] in
> @@ -366,7 +366,7 @@ def MFLR8 : XFXForm_1_ext<31, 339, 8, (
>
> let PPC970_Unit = 1 in { // FXU Operations.
> let Interpretation64Bit = 1 in {
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> let isCodeGenOnly = 1 in {
>
> let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
> @@ -517,7 +517,7 @@ defm MULHDU : XOForm_1r<31, 9, 0, (outs
> }
> } // Interpretation64Bit
>
> -let isCompare = 1, neverHasSideEffects = 1 in {
> +let isCompare = 1, hasSideEffects = 0 in {
> def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
> "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
> def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
> @@ -529,7 +529,7 @@ let isCompare = 1, neverHasSideEffects =
> IIC_IntCompare>, isPPC64;
> }
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
> "sld", "$rA, $rS, $rB", IIC_IntRotateD,
> [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
> @@ -600,7 +600,7 @@ def MULLI8 : DForm_2<7, (outs g8rc:$rD),
> [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
> }
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> let isCommutable = 1 in {
> defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
> (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
> @@ -661,7 +661,7 @@ def ISEL8 : AForm_4<31, 15,
> "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
> []>;
> } // Interpretation64Bit
> -} // neverHasSideEffects = 1
> +} // hasSideEffects = 0
> } // End FXU Operations.
>
>
> @@ -702,7 +702,7 @@ def LWAX_32 : XForm_1<31, 341, (outs gpr
> } // end fast-isel isCodeGenOnly
>
> // Update forms.
> -let mayLoad = 1, neverHasSideEffects = 1 in {
> +let mayLoad = 1, hasSideEffects = 0 in {
> let Interpretation64Bit = 1, isCodeGenOnly = 1 in
> def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
> (ins memri:$addr),
> @@ -750,7 +750,7 @@ def LWZX8 : XForm_1<31, 23, (outs g8rc:
>
>
> // Update forms.
> -let mayLoad = 1, neverHasSideEffects = 1 in {
> +let mayLoad = 1, hasSideEffects = 0 in {
> def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
> "lbzu $rD, $addr", IIC_LdStLoadUpd,
> []>, RegConstraint<"$addr.reg = $ea_result">,
> @@ -821,7 +821,7 @@ def LDBRX : XForm_1<31, 532, (outs g8rc
> "ldbrx $rD, $src", IIC_LdStLoad,
> [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
>
> -let mayLoad = 1, neverHasSideEffects = 1 in {
> +let mayLoad = 1, hasSideEffects = 0 in {
> def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
> "ldu $rD, $addr", IIC_LdStLDU,
> []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
> @@ -1006,7 +1006,7 @@ def : Pat<(pre_store i64:$rS, iPTR:$ptrr
> //
>
>
> -let PPC970_Unit = 3, neverHasSideEffects = 1,
> +let PPC970_Unit = 3, hasSideEffects = 0,
> Uses = [RM] in { // FPU Operations.
> defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
> "fcfid", "$frD, $frB", IIC_FPGeneral,
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Nov 25 18:46:26 2014
> @@ -1454,7 +1454,7 @@ def LFD : DForm_1<50, (outs f8rc:$rD), (
>
>
> // Unindexed (r+i) Loads with Update (preinc).
> -let mayLoad = 1, neverHasSideEffects = 1 in {
> +let mayLoad = 1, hasSideEffects = 0 in {
> def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
> "lbzu $rD, $addr", IIC_LdStLoadUpd,
> []>, RegConstraint<"$addr.reg = $ea_result">,
> @@ -1797,7 +1797,7 @@ def NOP_GT_PWR7 : DForm_4_fixedreg_zero<
> "ori 2, 2, 0", IIC_IntSimple, []>;
> }
>
> -let isCompare = 1, neverHasSideEffects = 1 in {
> +let isCompare = 1, hasSideEffects = 0 in {
> def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
> "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
> def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
> @@ -1805,7 +1805,7 @@ let isCompare = 1, neverHasSideEffects =
> }
> }
>
> -let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
> +let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
> let isCommutable = 1 in {
> defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
> "nand", "$rA, $rS, $rB", IIC_IntSimple,
> @@ -1848,7 +1848,7 @@ defm SRAW : XForm_6rc<31, 792, (outs gpr
> }
>
> let PPC970_Unit = 1 in { // FXU Operations.
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
> "srawi", "$rA, $rS, $SH", IIC_IntShift,
> [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
> @@ -1862,7 +1862,7 @@ defm EXTSH : XForm_11r<31, 922, (outs g
> "extsh", "$rA, $rS", IIC_IntSimple,
> [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
> }
> -let isCompare = 1, neverHasSideEffects = 1 in {
> +let isCompare = 1, hasSideEffects = 0 in {
> def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
> "cmpw $crD, $rA, $rB", IIC_IntCompare>;
> def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
> @@ -1872,7 +1872,7 @@ let isCompare = 1, neverHasSideEffects =
> let PPC970_Unit = 3 in { // FPU Operations.
> //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
> // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
> -let isCompare = 1, neverHasSideEffects = 1 in {
> +let isCompare = 1, hasSideEffects = 0 in {
> def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
> "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
> let Interpretation64Bit = 1, isCodeGenOnly = 1 in
> @@ -1881,7 +1881,7 @@ let isCompare = 1, neverHasSideEffects =
> }
>
> let Uses = [RM] in {
> - let neverHasSideEffects = 1 in {
> + let hasSideEffects = 0 in {
> defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
> "fctiw", "$frD, $frB", IIC_FPGeneral,
> []>;
> @@ -1902,7 +1902,7 @@ let Uses = [RM] in {
> [(set f32:$frD, (frnd f32:$frB))]>;
> }
>
> - let neverHasSideEffects = 1 in {
> + let hasSideEffects = 0 in {
> let Interpretation64Bit = 1, isCodeGenOnly = 1 in
> defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
> "frip", "$frD, $frB", IIC_FPGeneral,
> @@ -1939,13 +1939,13 @@ let Uses = [RM] in {
> /// often coalesced away and we don't want the dispatch group builder to think
> /// that they will fill slots (which could cause the load of a LSU reject to
> /// sneak into a d-group with a store).
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
> "fmr", "$frD, $frB", IIC_FPGeneral,
> []>, // (set f32:$frD, f32:$frB)
> PPC970_Unit_Pseudo;
>
> -let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
> +let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
> // These are artificially split into two different forms, for 4/8 byte FP.
> defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
> "fabs", "$frD, $frB", IIC_FPGeneral,
> @@ -1994,7 +1994,7 @@ defm FRSQRTES : XForm_26r<59, 26, (outs
>
> // XL-Form instructions. condition register logical ops.
> //
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
> "mcrf $BF, $BFA", IIC_BrMCR>,
> PPC970_DGroup_First, PPC970_Unit_CRU;
> @@ -2133,7 +2133,7 @@ let mayLoad = 1 in
> def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
> "#RESTORE_VRSAVE", []>;
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
> "mtocrf $FXM, $ST", IIC_BrMCRX>,
> PPC970_DGroup_First, PPC970_Unit_CRU;
> @@ -2150,7 +2150,7 @@ def MFOCRF: XFXForm_5a<31, 19, (outs gpr
> def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
> "mfcr $rT", IIC_SprMFCR>,
> PPC970_MicroCode, PPC970_Unit_CRU;
> -} // neverHasSideEffects = 1
> +} // hasSideEffects = 0
>
> // Pseudo instruction to perform FADD in round-to-zero mode.
> let usesCustomInserter = 1, Uses = [RM] in {
> @@ -2179,7 +2179,7 @@ let Uses = [RM] in {
> }
>
>
> -let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
> +let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
> // XO-Form instructions. Arithmetic instructions that can set overflow bit
> let isCommutable = 1 in
> defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
> @@ -2250,7 +2250,7 @@ defm SUBFZE : XOForm_3rc<31, 200, 0, (ou
> // A-Form instructions. Most of the instructions executed in the FPU are of
> // this type.
> //
> -let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
> +let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
> let Uses = [RM] in {
> let isCommutable = 1 in {
> defm FMADD : AForm_1r<63, 29,
> @@ -2346,7 +2346,7 @@ let Uses = [RM] in {
> }
> }
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> let PPC970_Unit = 1 in { // FXU Operations.
> let isSelect = 1 in
> def ISEL : AForm_4<31, 15,
> @@ -2382,7 +2382,7 @@ defm RLWNM : MForm_2r<23, (outs gprc:$r
> "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
> []>;
> }
> -} // neverHasSideEffects = 1
> +} // hasSideEffects = 0
>
> //===----------------------------------------------------------------------===//
> // PowerPC Instruction Patterns
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td Tue Nov 25 18:46:26 2014
> @@ -42,7 +42,7 @@ multiclass XX3Form_Rcr<bits<6> opcode, b
> def HasVSX : Predicate<"PPCSubTarget->hasVSX()">;
> let Predicates = [HasVSX] in {
> let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
> -let neverHasSideEffects = 1 in { // VSX instructions don't have side effects.
> +let hasSideEffects = 0 in { // VSX instructions don't have side effects.
> let Uses = [RM] in {
>
> // Load indexed instructions
> @@ -728,7 +728,7 @@ let Uses = [RM] in {
> def XXSPLTW : XX2Form_2<60, 164,
> (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM),
> "xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>;
> -} // neverHasSideEffects
> +} // hasSideEffects
>
> // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
> // instruction selection into a branch sequence.
>
> Modified: llvm/trunk/lib/Target/R600/R600Instructions.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600Instructions.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/R600Instructions.td (original)
> +++ llvm/trunk/lib/Target/R600/R600Instructions.td Tue Nov 25 18:46:26 2014
> @@ -1364,7 +1364,7 @@ def CONST_COPY : Instruction {
> let Pattern =
> [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
> let AsmString = "CONST_COPY";
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> let isAsCheapAsAMove = 1;
> let Itinerary = NullALU;
> }
>
> Modified: llvm/trunk/lib/Target/R600/SIInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrFormats.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/SIInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/R600/SIInstrFormats.td Tue Nov 25 18:46:26 2014
> @@ -567,7 +567,7 @@ class MTBUF <dag outs, dag ins, string a
> let EXP_CNT = 1;
> let MTBUF = 1;
>
> - let neverHasSideEffects = 1;
> + let hasSideEffects = 0;
> let UseNamedOperandTable = 1;
> }
>
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td Tue Nov 25 18:46:26 2014
> @@ -26,14 +26,14 @@ defm CondStoreF64 : CondStores<FP64, non
> //===----------------------------------------------------------------------===//
>
> // Load zero.
> -let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
> +let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1 in {
> def LZER : InherentRRE<"lzer", 0xB374, FP32, (fpimm0)>;
> def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>;
> def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>;
> }
>
> // Moves between two floating-point registers.
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def LER : UnaryRR <"le", 0x38, null_frag, FP32, FP32>;
> def LDR : UnaryRR <"ld", 0x28, null_frag, FP64, FP64>;
> def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>;
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Tue Nov 25 18:46:26 2014
> @@ -16,7 +16,7 @@ def ADJCALLSTACKDOWN : Pseudo<(outs), (i
> def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
> [(callseq_end timm:$amt1, timm:$amt2)]>;
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> // Takes as input the value of the stack pointer after a dynamic allocation
> // has been made. Sets the output to the address of the dynamically-
> // allocated area itself, skipping the outgoing arguments.
> @@ -263,7 +263,7 @@ def BASR : InstRR<0x0D, (outs), (ins GR
> //===----------------------------------------------------------------------===//
>
> // Register moves.
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> // Expands to LR, RISBHG or RISBLG, depending on the choice of registers.
> def LRMux : UnaryRRPseudo<"l", null_frag, GRX32, GRX32>,
> Requires<[FeatureHighWord]>;
> @@ -286,7 +286,7 @@ let Uses = [CC] in {
> }
>
> // Immediate moves.
> -let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
> +let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
> isReMaterializable = 1 in {
> // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF,
> // deopending on the choice of register.
> @@ -402,13 +402,13 @@ let mayLoad = 1, mayStore = 1, Defs = [C
> //===----------------------------------------------------------------------===//
>
> // 32-bit extensions from registers.
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def LBR : UnaryRRE<"lb", 0xB926, sext8, GR32, GR32>;
> def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
> }
>
> // 64-bit extensions from registers.
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def LGBR : UnaryRRE<"lgb", 0xB906, sext8, GR64, GR64>;
> def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
> def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
> @@ -452,7 +452,7 @@ let Defs = [CC], CCValues = 0xE, Compare
> //===----------------------------------------------------------------------===//
>
> // 32-bit extensions from registers.
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> // Expands to LLCR or RISB[LH]G, depending on the choice of registers.
> def LLCRMux : UnaryRRPseudo<"llc", zext8, GRX32, GRX32>,
> Requires<[FeatureHighWord]>;
> @@ -464,7 +464,7 @@ let neverHasSideEffects = 1 in {
> }
>
> // 64-bit extensions from registers.
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def LLGCR : UnaryRRE<"llgc", 0xB984, zext8, GR64, GR64>;
> def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
> def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
> @@ -546,7 +546,7 @@ def STMG : StoreMultipleRSY<"stmg", 0xEB
> //===----------------------------------------------------------------------===//
>
> // Byte-swapping register moves.
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def LRVR : UnaryRRE<"lrv", 0xB91F, bswap, GR32, GR32>;
> def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
> }
> @@ -566,7 +566,7 @@ def STRVG : StoreRXY<"strvg", 0xE32F, st
> //===----------------------------------------------------------------------===//
>
> // Load BDX-style addresses.
> -let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
> +let hasSideEffects = 0, isAsCheapAsAMove = 1, isReMaterializable = 1,
> DispKey = "la" in {
> let DispSize = "12" in
> def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
> @@ -580,7 +580,7 @@ let neverHasSideEffects = 1, isAsCheapAs
>
> // Load a PC-relative address. There's no version of this instruction
> // with a 16-bit offset, so there's no relaxation.
> -let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
> +let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
> isReMaterializable = 1 in {
> def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
> "larl\t$R1, $I2",
> @@ -1012,13 +1012,13 @@ def DLG : BinaryRXY<"dlg", 0xE387, z_u
> //===----------------------------------------------------------------------===//
>
> // Shift left.
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
> def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>;
> }
>
> // Logical shift right.
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
> def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>;
> }
> @@ -1030,7 +1030,7 @@ let Defs = [CC], CCValues = 0xE, Compare
> }
>
> // Rotate left.
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def RLL : BinaryRSY<"rll", 0xEB1D, rotl, GR32>;
> def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>;
> }
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Tue Nov 25 18:46:26 2014
> @@ -15,7 +15,7 @@
> //===----------------------------------------------------------------------===//
> // LEA - Load Effective Address
> let SchedRW = [WriteLEA] in {
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def LEA16r : I<0x8D, MRMSrcMem,
> (outs GR16:$dst), (ins i32mem:$src),
> "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize16;
> @@ -65,18 +65,18 @@ def MUL8r : I<0xF6, MRM4r, (outs), (in
> [(set AL, (mul AL, GR8:$src)),
> (implicit EFLAGS)], IIC_MUL8>, Sched<[WriteIMul]>;
> // AX,DX = AX*GR16
> -let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
> +let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
> def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
> "mul{w}\t$src",
> [], IIC_MUL16_REG>, OpSize16, Sched<[WriteIMul]>;
> // EAX,EDX = EAX*GR32
> -let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
> +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], hasSideEffects = 0 in
> def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
> "mul{l}\t$src",
> [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/],
> IIC_MUL32_REG>, OpSize32, Sched<[WriteIMul]>;
> // RAX,RDX = RAX*GR64
> -let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
> +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
> def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
> "mul{q}\t$src",
> [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
> @@ -91,7 +91,7 @@ def MUL8m : I<0xF6, MRM4m, (outs), (ins
> [(set AL, (mul AL, (loadi8 addr:$src))),
> (implicit EFLAGS)], IIC_MUL8>, SchedLoadReg<WriteIMulLd>;
> // AX,DX = AX*[mem16]
> -let mayLoad = 1, neverHasSideEffects = 1 in {
> +let mayLoad = 1, hasSideEffects = 0 in {
> let Defs = [AX,DX,EFLAGS], Uses = [AX] in
> def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
> "mul{w}\t$src",
> @@ -107,7 +107,7 @@ def MUL64m : RI<0xF7, MRM4m, (outs), (in
> "mul{q}\t$src", [], IIC_MUL64>, SchedLoadReg<WriteIMulLd>;
> }
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> // AL,AH = AL*GR8
> let Defs = [AL,EFLAGS,AX], Uses = [AL] in
> def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", [],
> @@ -145,7 +145,7 @@ let Defs = [RAX,RDX,EFLAGS], Uses = [RAX
> def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
> "imul{q}\t$src", [], IIC_IMUL64>, SchedLoadReg<WriteIMulLd>;
> }
> -} // neverHasSideEffects
> +} // hasSideEffects
>
>
> let Defs = [EFLAGS] in {
> @@ -1332,7 +1332,7 @@ let Predicates = [HasBMI] in {
> // MULX Instruction
> //
> multiclass bmi_mulx<string mnemonic, RegisterClass RC, X86MemOperand x86memop> {
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> let isCommutable = 1 in
> def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src),
> !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Tue Nov 25 18:46:26 2014
> @@ -32,7 +32,7 @@ def GetLo8XForm : SDNodeXForm<imm, [{
> // PIC base construction. This expands to code that looks like this:
> // call $next_inst
> // popl %destreg"
> -let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
> +let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in
> def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
> "", []>;
>
> @@ -259,7 +259,7 @@ def : Pat<(i64 0), (SUBREG_TO_REG (i64 0
> // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
> // that would make it more difficult to rematerialize.
> let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
> - isCodeGenOnly = 1, neverHasSideEffects = 1 in
> + isCodeGenOnly = 1, hasSideEffects = 0 in
> def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
> "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>;
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrExtension.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrExtension.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrExtension.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrExtension.td Tue Nov 25 18:46:26 2014
> @@ -11,7 +11,7 @@
> //
> //===----------------------------------------------------------------------===//
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> let Defs = [AX], Uses = [AL] in
> def CBW : I<0x98, RawFrm, (outs), (ins),
> "{cbtw|cbw}", [], IIC_CBW>, OpSize16; // AX = signext(AL)
> @@ -39,7 +39,7 @@ let neverHasSideEffects = 1 in {
>
>
> // Sign/Zero extenders
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
> "movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_R8>,
> TB, OpSize16, Sched<[WriteALU]>;
> @@ -47,7 +47,7 @@ let mayLoad = 1 in
> def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
> "movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_M8>,
> TB, OpSize16, Sched<[WriteALULd]>;
> -} // neverHasSideEffects = 1
> +} // hasSideEffects = 0
> def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
> "movs{bl|x}\t{$src, $dst|$dst, $src}",
> [(set GR32:$dst, (sext GR8:$src))], IIC_MOVSX>, TB,
> @@ -65,7 +65,7 @@ def MOVSX32rm16: I<0xBF, MRMSrcMem, (out
> [(set GR32:$dst, (sextloadi32i16 addr:$src))], IIC_MOVSX>,
> OpSize32, TB, Sched<[WriteALULd]>;
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
> "movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_R8>,
> TB, OpSize16, Sched<[WriteALU]>;
> @@ -73,7 +73,7 @@ let mayLoad = 1 in
> def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
> "movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_M8>,
> TB, OpSize16, Sched<[WriteALULd]>;
> -} // neverHasSideEffects = 1
> +} // hasSideEffects = 0
> def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
> "movz{bl|x}\t{$src, $dst|$dst, $src}",
> [(set GR32:$dst, (zext GR8:$src))], IIC_MOVZX>, TB,
> @@ -94,7 +94,7 @@ def MOVZX32rm16: I<0xB7, MRMSrcMem, (out
> // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
> // except that they use GR32_NOREX for the output operand register class
> // instead of GR32. This allows them to operate on h registers on x86-64.
> -let neverHasSideEffects = 1, isCodeGenOnly = 1 in {
> +let hasSideEffects = 0, isCodeGenOnly = 1 in {
> def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
> (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src),
> "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrFMA.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrFMA.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrFMA.td Tue Nov 25 18:46:26 2014
> @@ -69,7 +69,7 @@ multiclass fma3p_forms<bits<8> opc132, b
> /* IsRVariantCommutable */ 1,
> /* IsMVariantCommutable */ 1,
> Op>;
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> defm r132 : fma3p_rm<opc132,
> !strconcat(OpcodeStr, "132", PackTy),
> MemFrag128, MemFrag256, OpTy128, OpTy256>;
> @@ -81,7 +81,7 @@ let neverHasSideEffects = 1 in {
> MemFrag128, MemFrag256, OpTy128, OpTy256,
> /* IsRVariantCommutable */ 1,
> /* IsMVariantCommutable */ 0>;
> -} // neverHasSideEffects = 1
> +} // hasSideEffects = 0
> }
>
> // Fused Multiply-Add
> @@ -155,7 +155,7 @@ multiclass fma3s_forms<bits<8> opc132, b
> SDNode OpNode, RegisterClass RC, ValueType OpVT,
> X86MemOperand x86memop, Operand memop, PatFrag mem_frag,
> ComplexPattern mem_cpat> {
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> defm r132 : fma3s_rm<opc132, !strconcat(OpStr, "132", PackTy),
> x86memop, RC, OpVT, mem_frag>;
> // See the other defm of r231 for the explanation regarding the
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Tue Nov 25 18:46:26 2014
> @@ -282,7 +282,7 @@ defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt"
> defm SIN : FPUnary<fsin, MRM_FE, "fsin">;
> defm COS : FPUnary<fcos, MRM_FF, "fcos">;
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
> def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
> def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
> @@ -415,7 +415,7 @@ def ST_Fp80m64 : FpI_<(outs), (ins f64me
> [(truncstoref64 RFP80:$src, addr:$op)]>;
> // FST does not support 80-bit memory target; FSTP must be used.
>
> -let mayStore = 1, neverHasSideEffects = 1 in {
> +let mayStore = 1, hasSideEffects = 0 in {
> def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
> def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
> def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
> @@ -424,7 +424,7 @@ def ST_FpP80m64 : FpI_<(outs), (ins f64
> }
> def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
> [(store RFP80:$src, addr:$op)]>;
> -let mayStore = 1, neverHasSideEffects = 1 in {
> +let mayStore = 1, hasSideEffects = 0 in {
> def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
> def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
> def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Nov 25 18:46:26 2014
> @@ -905,7 +905,7 @@ def trunc_su : PatFrag<(ops node:$src),
> //
>
> // Nop
> -let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
> +let hasSideEffects = 0, SchedRW = [WriteZero] in {
> def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
> def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
> "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
> @@ -919,12 +919,12 @@ def ENTER : Ii16<0xC8, RawFrmImm8, (outs
> "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
>
> let SchedRW = [WriteALU] in {
> -let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
> +let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
> def LEAVE : I<0xC9, RawFrm,
> (outs), (ins), "leave", [], IIC_LEAVE>,
> Requires<[Not64BitMode]>;
>
> -let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
> +let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
> def LEAVE64 : I<0xC9, RawFrm,
> (outs), (ins), "leave", [], IIC_LEAVE>,
> Requires<[In64BitMode]>;
> @@ -934,7 +934,7 @@ def LEAVE64 : I<0xC9, RawFrm,
> // Miscellaneous Instructions.
> //
>
> -let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
> +let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
> let mayLoad = 1, SchedRW = [WriteLoad] in {
> def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
> IIC_POP_REG16>, OpSize16;
> @@ -990,7 +990,7 @@ def PUSHF32 : I<0x9C, RawFrm, (outs), (
> } // mayStore, SchedRW
> }
>
> -let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
> +let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
> let mayLoad = 1, SchedRW = [WriteLoad] in {
> def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
> IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
> @@ -1009,7 +1009,7 @@ def PUSH64rmm: I<0xFF, MRM6m, (outs), (i
> } // mayStore, SchedRW
> }
>
> -let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1,
> +let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
> SchedRW = [WriteStore] in {
> def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
> "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
> @@ -1021,22 +1021,22 @@ def PUSH64i32 : Ii32S<0x68, RawFrm, (ou
> Requires<[In64BitMode]>;
> }
>
> -let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
> +let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
> def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
> OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
> -let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
> +let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
> def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
> OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
>
> let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
> - mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
> + mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
> def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
> OpSize32, Requires<[Not64BitMode]>;
> def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
> OpSize16, Requires<[Not64BitMode]>;
> }
> let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
> - mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
> + mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
> def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
> OpSize32, Requires<[Not64BitMode]>;
> def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
> @@ -1166,7 +1166,7 @@ def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs
> // Move Instructions.
> //
> let SchedRW = [WriteMove] in {
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
> "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
> def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
> @@ -1371,17 +1371,17 @@ def MOV64mr : RI<0x89, MRMDestMem, (outs
> // that they can be used for copying and storing h registers, which can't be
> // encoded when a REX prefix is present.
> let isCodeGenOnly = 1 in {
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def MOV8rr_NOREX : I<0x88, MRMDestReg,
> (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
> "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
> Sched<[WriteMove]>;
> -let mayStore = 1, neverHasSideEffects = 1 in
> +let mayStore = 1, hasSideEffects = 0 in
> def MOV8mr_NOREX : I<0x88, MRMDestMem,
> (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
> "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
> IIC_MOV_MEM>, Sched<[WriteStore]>;
> -let mayLoad = 1, neverHasSideEffects = 1,
> +let mayLoad = 1, hasSideEffects = 0,
> canFoldAsLoad = 1, isReMaterializable = 1 in
> def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
> (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
> @@ -1395,7 +1395,7 @@ let SchedRW = [WriteALU] in {
> let Defs = [EFLAGS], Uses = [AH] in
> def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
> [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
> -let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
> +let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
> def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
> IIC_AHF>; // AH = flags
> } // SchedRW
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Tue Nov 25 18:46:26 2014
> @@ -257,7 +257,7 @@ def MMX_MOVD64from64rr : MMXRI<0x7E, MRM
> "movd\t{$src, $dst|$dst, $src}",
> [(set GR64:$dst,
> (bitconvert VR64:$src))], IIC_MMX_MOV_REG_MM>;
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
> "movq\t{$src, $dst|$dst, $src}", [],
> IIC_MMX_MOVQ_RR>;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Nov 25 18:46:26 2014
> @@ -809,7 +809,7 @@ multiclass sse12_mov_packed<bits<8> opc,
> string asm, Domain d,
> OpndItins itins,
> bit IsReMaterializable = 1> {
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
> !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
> Sched<[WriteFShuffle]>;
> @@ -1477,7 +1477,7 @@ multiclass sse12_cvt_s<bits<8> opc, Regi
> multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
> X86MemOperand x86memop, string asm, Domain d,
> OpndItins itins> {
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
> [], itins.rr, d>, Sched<[itins.Sched]>;
> let mayLoad = 1 in
> @@ -1488,7 +1488,7 @@ let neverHasSideEffects = 1 in {
>
> multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
> X86MemOperand x86memop, string asm> {
> -let neverHasSideEffects = 1, Predicates = [UseAVX] in {
> +let hasSideEffects = 0, Predicates = [UseAVX] in {
> def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
> !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
> Sched<[WriteCvtI2F]>;
> @@ -1497,7 +1497,7 @@ let neverHasSideEffects = 1, Predicates
> (ins DstRC:$src1, x86memop:$src),
> !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
> Sched<[WriteCvtI2FLd, ReadAfterLd]>;
> -} // neverHasSideEffects = 1
> +} // hasSideEffects = 0
> }
>
> let Predicates = [UseAVX] in {
> @@ -1804,7 +1804,7 @@ def : InstAlias<"cvtsd2si{q}\t{$src, $ds
> /// SSE 2 Only
>
> // Convert scalar double to scalar single
> -let neverHasSideEffects = 1, Predicates = [UseAVX] in {
> +let hasSideEffects = 0, Predicates = [UseAVX] in {
> def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
> (ins FR64:$src1, FR64:$src2),
> "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
> @@ -1869,7 +1869,7 @@ def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
>
> // Convert scalar single to scalar double
> // SSE2 instructions with XS prefix
> -let neverHasSideEffects = 1, Predicates = [UseAVX] in {
> +let hasSideEffects = 0, Predicates = [UseAVX] in {
> def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
> (ins FR32:$src1, FR32:$src2),
> "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> @@ -2191,7 +2191,7 @@ def CVTPS2PDrm : I<0x5A, MRMSrcMem, (out
>
> // Convert Packed DW Integers to Packed Double FP
> let Predicates = [HasAVX] in {
> -let neverHasSideEffects = 1, mayLoad = 1 in
> +let hasSideEffects = 0, mayLoad = 1 in
> def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
> "vcvtdq2pd\t{$src, $dst|$dst, $src}",
> []>, VEX, Sched<[WriteCvtI2FLd]>;
> @@ -2213,7 +2213,7 @@ def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg
> Sched<[WriteCvtI2F]>;
> }
>
> -let neverHasSideEffects = 1, mayLoad = 1 in
> +let hasSideEffects = 0, mayLoad = 1 in
> def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
> "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
> IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
> @@ -4026,7 +4026,7 @@ def STMXCSR : PSI<0xAE, MRM3m, (outs), (
>
> let ExeDomain = SSEPackedInt in { // SSE integer instructions
>
> -let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
> +let hasSideEffects = 0, SchedRW = [WriteMove] in {
> def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
> VEX;
> @@ -4061,7 +4061,7 @@ def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestR
> }
>
> let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
> - neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
> + hasSideEffects = 0, SchedRW = [WriteLoad] in {
> def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
> "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
> VEX;
> @@ -4078,7 +4078,7 @@ let Predicates = [HasAVX] in {
> }
> }
>
> -let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
> +let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
> def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
> (ins i128mem:$dst, VR128:$src),
> "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
> @@ -4098,7 +4098,7 @@ def VMOVDQUYmr : I<0x7F, MRMDestMem, (ou
> }
>
> let SchedRW = [WriteMove] in {
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
>
> @@ -4119,7 +4119,7 @@ def MOVDQUrr_REV : I<0x7F, MRMDestReg,
> } // SchedRW
>
> let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
> - neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
> + hasSideEffects = 0, SchedRW = [WriteLoad] in {
> def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
> "movdqa\t{$src, $dst|$dst, $src}",
> [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
> @@ -4131,7 +4131,7 @@ def MOVDQUrm : I<0x6F, MRMSrcMem, (out
> XS, Requires<[UseSSE2]>;
> }
>
> -let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
> +let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
> def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
> "movdqa\t{$src, $dst|$dst, $src}",
> [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
> @@ -5414,7 +5414,7 @@ let Predicates = [UseSSE3] in {
> //===---------------------------------------------------------------------===//
>
> multiclass sse3_replicate_dfp<string OpcodeStr> {
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
> [], IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
> @@ -5987,7 +5987,7 @@ defm PMULHRSW : SS3I_binop_rm_int<0x0
> //===---------------------------------------------------------------------===//
>
> multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
> - let neverHasSideEffects = 1 in {
> + let hasSideEffects = 0 in {
> def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
> (ins VR128:$src1, VR128:$src2, i8imm:$src3),
> !if(Is2Addr,
> @@ -6007,7 +6007,7 @@ multiclass ssse3_palignr<string asm, bit
> }
>
> multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
> - let neverHasSideEffects = 1 in {
> + let hasSideEffects = 0 in {
> def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
> (ins VR256:$src1, VR256:$src2, i8imm:$src3),
> !strconcat(asm,
> @@ -6655,7 +6655,7 @@ multiclass SS41I_extract8<bits<8> opc, s
> [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
> imm:$src2))]>,
> Sched<[WriteShuffle]>;
> - let neverHasSideEffects = 1, mayStore = 1,
> + let hasSideEffects = 0, mayStore = 1,
> SchedRW = [WriteShuffleLd, WriteRMW] in
> def mr : SS4AIi8<opc, MRMDestMem, (outs),
> (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
> @@ -6680,7 +6680,7 @@ multiclass SS41I_extract16<bits<8> opc,
> "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
> []>, Sched<[WriteShuffle]>;
>
> - let neverHasSideEffects = 1, mayStore = 1,
> + let hasSideEffects = 0, mayStore = 1,
> SchedRW = [WriteShuffleLd, WriteRMW] in
> def mr : SS4AIi8<opc, MRMDestMem, (outs),
> (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
> @@ -7937,7 +7937,7 @@ multiclass pcmpistrm_SS42AI<string asm>
> []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
> }
>
> -let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
> +let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
> let Predicates = [HasAVX] in
> defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
> defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
> @@ -7972,7 +7972,7 @@ multiclass SS42AI_pcmpestrm<string asm>
> []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
> }
>
> -let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
> +let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
> let Predicates = [HasAVX] in
> defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
> defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
> @@ -8007,7 +8007,7 @@ multiclass SS42AI_pcmpistri<string asm>
> []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
> }
>
> -let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
> +let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
> let Predicates = [HasAVX] in
> defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
> defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
> @@ -8043,7 +8043,7 @@ multiclass SS42AI_pcmpestri<string asm>
> []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
> }
>
> -let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
> +let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
> let Predicates = [HasAVX] in
> defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
> defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
> @@ -8422,7 +8422,7 @@ def : Pat<(int_x86_avx_vbroadcastf128_ps
> //===----------------------------------------------------------------------===//
> // VINSERTF128 - Insert packed floating-point values
> //
> -let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
> +let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
> def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
> (ins VR256:$src1, VR128:$src2, i8imm:$src3),
> "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
> @@ -8496,7 +8496,7 @@ def : Pat<(vinsert128_insert:$ins (v16i1
> //===----------------------------------------------------------------------===//
> // VEXTRACTF128 - Extract packed floating-point values
> //
> -let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
> +let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
> def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
> (ins VR256:$src1, i8imm:$src2),
> "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> @@ -8756,7 +8756,7 @@ multiclass f16c_ph2ps<RegisterClass RC,
> "vcvtph2ps\t{$src, $dst|$dst, $src}",
> [(set RC:$dst, (Int VR128:$src))]>,
> T8PD, VEX, Sched<[WriteCvtF2F]>;
> - let neverHasSideEffects = 1, mayLoad = 1 in
> + let hasSideEffects = 0, mayLoad = 1 in
> def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
> "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
> Sched<[WriteCvtF2FLd]>;
> @@ -8768,7 +8768,7 @@ multiclass f16c_ps2ph<RegisterClass RC,
> "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
> TAPD, VEX, Sched<[WriteCvtF2F]>;
> - let neverHasSideEffects = 1, mayStore = 1,
> + let hasSideEffects = 0, mayStore = 1,
> SchedRW = [WriteCvtF2FLd, WriteRMW] in
> def mr : Ii8<0x1D, MRMDestMem, (outs),
> (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
> @@ -9122,7 +9122,7 @@ def : Pat<(v8i32 (X86VPerm2x128 VR256:$s
> //===----------------------------------------------------------------------===//
> // VINSERTI128 - Insert packed integer values
> //
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
> (ins VR256:$src1, VR128:$src2, i8imm:$src3),
> "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
> @@ -9182,7 +9182,7 @@ def VEXTRACTI128rr : AVX2AIi8<0x39, MRMD
> [(set VR128:$dst,
> (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
> Sched<[WriteShuffle256]>, VEX, VEX_L;
> -let neverHasSideEffects = 1, mayStore = 1 in
> +let hasSideEffects = 0, mayStore = 1 in
> def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
> (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
> "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td Tue Nov 25 18:46:26 2014
> @@ -859,7 +859,7 @@ def ROT64L2R_imm8 : SDNodeXForm<imm, [{
> }]>;
>
> multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> {
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2),
> !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
> []>, TAXD, VEX, Sched<[WriteShift]>;
> @@ -872,7 +872,7 @@ let neverHasSideEffects = 1 in {
> }
>
> multiclass bmi_shift<string asm, RegisterClass RC, X86MemOperand x86memop> {
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
> !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
> VEX_4VOp3, Sched<[WriteShift]>;
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=222801&r1=222800&r2=222801&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Tue Nov 25 18:46:26 2014
> @@ -381,7 +381,7 @@ def Int_MemBarrier : PseudoInstXCore<(ou
> // Three operand short
> defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;
> defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">;
> def LSS_3r : F3R_np<0b11000, "lss">;
> def LSU_3r : F3R_np<0b11001, "lsu">;
> @@ -432,7 +432,7 @@ def LDAWF_l3r : _FL3R<0b000111100, (outs
> [(set GRRegs:$dst,
> (ldawf GRRegs:$addr, GRRegs:$offset))]>;
>
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst),
> (ins GRRegs:$addr, i32imm:$offset),
> "ldaw $dst, $addr[$offset]", []>;
> @@ -443,7 +443,7 @@ def LDAWB_l3r : _FL3R<0b001001100, (outs
> [(set GRRegs:$dst,
> (ldawb GRRegs:$addr, GRRegs:$offset))]>;
>
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst),
> (ins GRRegs:$addr, i32imm:$offset),
> "ldaw $dst, $addr[-$offset]", []>;
> @@ -538,7 +538,7 @@ def LMUL_l6r : _FL6R<
> // Register - U6
>
> //let Uses = [DP] in ...
> -let neverHasSideEffects = 1, isReMaterializable = 1 in
> +let hasSideEffects = 0, isReMaterializable = 1 in
> def LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b),
> "ldaw $a, dp[$b]", []>;
>
> @@ -564,7 +564,7 @@ def STWDP_lru6 : _FLRU6<0b010100, (outs)
> [(store RRegs:$a, (dprelwrapper tglobaladdr:$b))]>;
>
> //let Uses = [CP] in ..
> -let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in {
> +let mayLoad = 1, isReMaterializable = 1, hasSideEffects = 0 in {
> def LDWCP_ru6 : _FRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b),
> "ldw $a, cp[$b]", []>;
> def LDWCP_lru6: _FLRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b),
> @@ -593,7 +593,7 @@ def LDWSP_lru6 : _FLRU6<0b010111, (outs
> [(set RRegs:$a, (XCoreLdwsp immU16:$b))]>;
> }
>
> -let neverHasSideEffects = 1 in {
> +let hasSideEffects = 0 in {
> def LDAWSP_ru6 : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
> "ldaw $a, sp[$b]", []>;
>
> @@ -628,7 +628,7 @@ defm BRBF: FRU6_LRU6_backwards_branch<0b
>
> // U6
> let Defs = [SP], Uses = [SP] in {
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">;
>
> let mayStore = 1 in
> @@ -639,7 +639,7 @@ defm RETSP : FU6_LU6<0b0111011111, "rets
> }
> }
>
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> defm EXTDP : FU6_LU6_np<0b0111001110, "extdp">;
>
> let Uses = [R11], isCall=1 in
> @@ -656,7 +656,7 @@ def BRFU_lu6 : _FLU6<0b0111001100, (outs
> }
>
> //let Uses = [CP] in ...
> -let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
> +let Defs = [R11], hasSideEffects = 0, isReMaterializable = 1 in
> def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]",
> []>;
>
> @@ -690,17 +690,17 @@ defm KRESTSP : FU6_LU6_np<0b0111101111,
> // U10
>
> let Defs = [R11], isReMaterializable = 1 in {
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def LDAPF_u10 : _FU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", []>;
>
> def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a",
> [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
>
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def LDAPB_u10 : _FU10<0b110111, (outs), (ins pcrel_imm_neg:$a), "ldap r11, $a",
> []>;
>
> -let neverHasSideEffects = 1 in
> +let hasSideEffects = 0 in
> def LDAPB_lu10 : _FLU10<0b110111, (outs), (ins pcrel_imm_neg:$a),
> "ldap r11, $a",
> [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
> @@ -729,7 +729,7 @@ def BLRB_lu10 : _FLU10<0b110101, (outs),
> }
>
> let Defs = [R11], mayLoad = 1, isReMaterializable = 1,
> - neverHasSideEffects = 1 in {
> + hasSideEffects = 0 in {
> def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>;
>
> def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]",
> @@ -772,7 +772,7 @@ def ANDNOT_2r :
> [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
> }
>
> -let isReMaterializable = 1, neverHasSideEffects = 1 in
> +let isReMaterializable = 1, hasSideEffects = 0 in
> def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size),
> "mkmsk $dst, $size", []>;
>
> @@ -972,13 +972,13 @@ def BR_JT32 : PseudoInstXCore<(outs), (i
> let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
> def BRU_1r : _F1R<0b001010, (outs), (ins GRRegs:$a), "bru $a", []>;
>
> -let Defs=[SP], neverHasSideEffects=1 in
> +let Defs=[SP], hasSideEffects=0 in
> def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>;
>
> -let neverHasSideEffects=1 in
> +let hasSideEffects=0 in
> def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>;
>
> -let neverHasSideEffects=1 in
> +let hasSideEffects=0 in
> def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>;
>
> let hasCtrlDep = 1 in
>
>
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