[llvm] r222791 - [Hexagon] Adding NOP encoding bits.
Colin LeMahieu
colinl at codeaurora.org
Tue Nov 25 13:23:08 PST 2014
Author: colinl
Date: Tue Nov 25 15:23:07 2014
New Revision: 222791
URL: http://llvm.org/viewvc/llvm-project?rev=222791&view=rev
Log:
[Hexagon] Adding NOP encoding bits.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=222791&r1=222790&r2=222791&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Tue Nov 25 15:23:07 2014
@@ -409,10 +409,11 @@ def AND_ri : ALU32_ri<(outs IntRegs:$dst
s10ExtPred:$src2))]>, ImmRegRel;
// Nop.
-let neverHasSideEffects = 1, isCodeGenOnly = 0 in
-def NOP : ALU32_rr<(outs), (ins),
- "nop",
- []>;
+let hasSideEffects = 0 in
+def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
+ let IClass = 0b0111;
+ let Inst{27-24} = 0b1111;
+}
// Rd32=sub(#s10,Rs32)
let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp?rev=222791&r1=222790&r2=222791&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp Tue Nov 25 15:23:07 2014
@@ -97,7 +97,7 @@ void HexagonInstPrinter::printInst(const
HexagonMCInst Nop;
StringRef NoAnnot;
- Nop.setOpcode (Hexagon::NOP);
+ Nop.setOpcode (Hexagon::A2_nop);
Nop.setPacketStart (MI->isPacketStart());
printInst (&Nop, O, NoAnnot);
}
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