[llvm] r222712 - [PowerPC] Add the 'attn' instruction

[Hal Finkel]

Author: hfinkel
Date: Mon Nov 24 18:30:11 2014
New Revision: 222712

URL: http://llvm.org/viewvc/llvm-project?rev=222712&view=rev
Log:
[PowerPC] Add the 'attn' instruction

The attn instruction is not part of the Power ISA, but is documented in the A2
user manual, and is accepted by the GNU assembler for the A2 and the POWER4+.
Reported as part of PR21650.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
    llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
    llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td?rev=222712&r1=222711&r2=222712&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td Mon Nov 24 18:30:11 2014
@@ -385,6 +385,12 @@ class XForm_tlb<bits<10> xo, dag OOL, da
   let RST = 0;
 }
 
+class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+                 InstrItinClass itin>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  let Inst{21-30} = xo;
+}
+
 // This is the same as XForm_base_r3xo, but the first two operands are swapped
 // when code is emitted.
 class XForm_base_r3xo_swapped

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=222712&r1=222711&r2=222712&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Mon Nov 24 18:30:11 2014
@@ -3232,6 +3232,8 @@ def MFDCR : XFXForm_1<31, 323, (outs gpr
 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
                       "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
 
+def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
+
 //===----------------------------------------------------------------------===//
 // PowerPC Assembler Instruction Aliases
 //

Modified: llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt?rev=222712&r1=222711&r2=222712&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt (original)
+++ llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt Mon Nov 24 18:30:11 2014
@@ -2274,3 +2274,7 @@
 
 # CHECK: rfid
 0x4c 0x00 0x00 0x24
+
+# CHECK: attn
+0x00 0x00 0x02 0x00
+

Modified: llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s?rev=222712&r1=222711&r2=222712&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s (original)
+++ llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s Mon Nov 24 18:30:11 2014
@@ -3633,3 +3633,9 @@
 # CHECK-BE: mtspr 280, 2                     # encoding: [0x7c,0x58,0x43,0xa6]
 # CHECK-LE: mtspr 280, 2                     # encoding: [0xa6,0x43,0x58,0x7c]
             mtasr 2
+
+# Processor-Specific Instructions
+# CHECK-BE: attn                             # encoding: [0x00,0x00,0x02,0x00]
+# CHECK-LE: attn                             # encoding: [0x00,0x02,0x00,0x00]
+            attn
+