[PATCH] [x86] Add a feature flag for slow 32-byte unaligned memory accesses.

[Sanjay Patel]

Hi qcolombet, hfinkel, andreadb, nadav,

This patch adds a feature flag to avoid unaligned 32-byte load/store AVX codegen for Sandy Bridge and Ivy Bridge. There is no functionality change intended for those chips. Previously, the absence of AVX2 was being used as a proxy to detect this feature. But that hindered codegen for AVX-enabled AMD chips such as btver2 that do not have the 32-byte unaligned access slowdown.

More detailed performance measurements are included in PR21541 ( http://llvm.org/bugs/show_bug.cgi?id=21541 ).

http://reviews.llvm.org/D6355

Files:
  lib/Target/X86/X86.td
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86Subtarget.cpp
  lib/Target/X86/X86Subtarget.h
  test/CodeGen/X86/2012-05-19-avx2-store.ll
  test/CodeGen/X86/unaligned-32-byte-memops.ll
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