[PATCH] [X86] Improved lowering of v4x32 build_vector dag nodes.

[Quentin Colombet]

Hi Andrea,

LGTM.

Thanks,
-Quentin

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:5784
@@ -5775,1 +5783,3 @@
+    if (Zeroable[EltIdx]) {
+      Mask[EltIdx] = EltIdx+4;
       continue;
----------------
Just add a comment that the zero vector will be on the RHS, that’s why it is EltIdx + 4.

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:5789
@@ +5788,3 @@
+    Elt = Op->getOperand(EltIdx);
+    EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
+    if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
----------------
Add a comment that by construction Elt is a EXTRACT_VECTOR_ELT with constant index.

http://reviews.llvm.org/D6311