[PATCH][AVX512] Add 512b integer shift by variable patterns and intrinsics

[Demikhovsky, Elena]

Hi Cam,

The GCC built-in names are incorrect. Please look here https://gcc.gnu.org/svn/gcc/branches/avx512-vlbwdq/gcc/config/i386/avx512fintrin.h
 for the reference.

I also suggest to put two more multiclasses in the middle, we'll need to add "W" form as well.

+defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl, v4i32, bc_v4i32, v16i32_info>, 
+                           EVEX_V512, EVEX_CD8<32, CD8VQ>;
+defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl, v2i64, bc_v2i64, v8i64_info>,
+                           EVEX_V512, EVEX_CD8<64, CD8VQ>, VEX_W;

I suggest something to write like this:

multiclass avx512_varshift_sizes <>{
defm Z:           avx512_shift_rrm<opc..>, EVEX_V512
defm Z256:     avx512_shift_rrm<opc..>, EVEX_V256
defm Z128:     avx512_shift_rrm<opc.. ..>, EVEX_V128
}

multiclass avx512_varshift_types < bits<8> opcd, bits<8> opcq, bits<8> opcqw, string OpcodeStr, SDNode OpNode > {
defm D: avx512_varshift_sizes <opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32, .. >, EVEX_CD8<32, CD8VQ>
defm Q: avx512_varshift_sizes <opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64 ..>, EVEX_CD8<64, CD8VQ>, VEX_W
defm W:
}
defm VPSRL : avx512_varshift_types <0xD2, 0xD3, 0xD1 




-  Elena


-----Original Message-----
From: Cameron McInally [mailto:cameron.mcinally at nyu.edu] 
Sent: Tuesday, November 18, 2014 22:34
To: llvm-commits at cs.uiuc.edu
Cc: Demikhovsky, Elena; Robert Khasanov
Subject: [PATCH][AVX512] Add 512b integer shift by variable patterns and intrinsics

Hey guys,

Attached is a patch to support 512b integer shift by variable intrinsics for AVX512.

Thanks,
Cam
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