[llvm] r222073 - R600: Fix 64-bit integer division

[Tom Stellard]

Author: tstellar
Date: Fri Nov 14 19:07:57 2014
New Revision: 222073

URL: http://llvm.org/viewvc/llvm-project?rev=222073&view=rev
Log:
R600: Fix 64-bit integer division

This fixes a failure in one of the oclconform tests.

Patch by: Jan Vesely

Modified:
    llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp

Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=222073&r1=222072&r2=222073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp Fri Nov 14 19:07:57 2014
@@ -1618,7 +1618,7 @@ void AMDGPUTargetLowering::LowerUDIVREM6
     SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
 
     SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
-    SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETGE);
+    SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
 
     DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
 
@@ -1626,7 +1626,7 @@ void AMDGPUTargetLowering::LowerUDIVREM6
 
     SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
 
-    REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETGE);
+    REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
     REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
     REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
   }