[PATCH] [AArch64] Load Balancing for AES instructions on Cortex-A57

[Z. Zheng]

James, 

Thanks for the feed back. To make sure I understand correctly: the way we build chains (mul-mla or aes) is forward, which is fine.

But it's better to color the chains backward for the G->getLast() to handle tied dest register. This would requires us to iterate from the last instructions to the first of a chain in ColorChain() and make appropriate changes to scavengeRegister().

Is this the plan you envisioned to add back support for MLAv2f32?

Thanks,
Zhaoshi

http://reviews.llvm.org/D6154