[llvm] r221961 - X86: use getConstant rather than getTargetConstant behind BUILD_VECTOR.

[Quentin Colombet]

Nice catch.

Thanks,
-Quentin

On Nov 13, 2014, at 5:30 PM, Tim Northover <tnorthover at apple.com> wrote:

> Author: tnorthover
> Date: Thu Nov 13 19:30:14 2014
> New Revision: 221961
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=221961&view=rev
> Log:
> X86: use getConstant rather than getTargetConstant behind BUILD_VECTOR.
> 
> getTargetConstant should only be used when you can guarantee the instruction
> selected will be able to cope with the raw value. BUILD_VECTOR is rather too
> generic for this so we should use getConstant instead. In that case, an
> instruction can still consume the constant, but if it doesn't it'll be
> materialised through its own round of ISel.
> 
> Should fix PR21352.
> 
> Modified:
>    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>    llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v16.ll
> 
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=221961&r1=221960&r2=221961&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Nov 13 19:30:14 2014
> @@ -5062,32 +5062,32 @@ static SDValue getZeroVector(EVT VT, con
>   SDValue Vec;
>   if (VT.is128BitVector()) {  // SSE
>     if (Subtarget->hasSSE2()) {  // SSE2
> -      SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
> +      SDValue Cst = DAG.getConstant(0, MVT::i32);
>       Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
>     } else { // SSE1
> -      SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
> +      SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
>       Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
>     }
>   } else if (VT.is256BitVector()) { // AVX
>     if (Subtarget->hasInt256()) { // AVX2
> -      SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
> +      SDValue Cst = DAG.getConstant(0, MVT::i32);
>       SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
>       Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
>     } else {
>       // 256-bit logic and arithmetic instructions in AVX are all
>       // floating-point, no support for integer ops. Emit fp zeroed vectors.
> -      SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
> +      SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
>       SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
>       Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
>     }
>   } else if (VT.is512BitVector()) { // AVX-512
> -      SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
> +      SDValue Cst = DAG.getConstant(0, MVT::i32);
>       SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
>                         Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
>       Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
>   } else if (VT.getScalarType() == MVT::i1) {
>     assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
> -    SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
> +    SDValue Cst = DAG.getConstant(0, MVT::i1);
>     SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
>     return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
>   } else
> @@ -5104,7 +5104,7 @@ static SDValue getOnesVector(MVT VT, boo
>                              SDLoc dl) {
>   assert(VT.isVector() && "Expected a vector type");
> 
> -  SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
> +  SDValue Cst = DAG.getConstant(~0U, MVT::i32);
>   SDValue Vec;
>   if (VT.is256BitVector()) {
>     if (HasInt256) { // AVX2
> 
> Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v16.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v16.ll?rev=221961&r1=221960&r2=221961&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v16.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v16.ll Thu Nov 13 19:30:14 2014
> @@ -1219,3 +1219,14 @@ entry:
> 
>   ret <16 x i8> %s.2.0
> }
> +
> +define void @constant_gets_selected() {
> +; ALL-LABEL: constant_gets_selected:
> +; ALL-NOT movd $0, {{%xmm[0-9]+}}
> +  %weird_zero = bitcast <4 x i32> zeroinitializer to <16 x i8>
> +  %shuffle.i = shufflevector <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0>, <16 x i8> %weird_zero, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
> +  %weirder_zero = bitcast <16 x i8> %shuffle.i to <4 x i32>
> +  store <4 x i32> %weirder_zero, <4 x i32>* undef, align 16
> +  store <4 x i32> zeroinitializer, <4 x i32>* undef, align 16
> +  ret void
> +}
> 
> 
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