[PATCH] Change order of tablegen generated fastisel instruction code to be based on instruction complexity

[Eric Christopher]

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Comment at: /home/seurer/llvm/llvm-oneoff/utils/TableGen/FastISelEmitter.cpp:669
@@ -646,1 +668,3 @@
+                               "  predicate: " + PredicateCheck);
+                }
                 OS << "  if (" + PredicateCheck + ") {\n";
----------------
seurer wrote:
> echristo wrote:
> > seurer wrote:
> > > Should this PrintWarning be an PrintError or an assert?  The X86 target actually hits this at least once so perhaps there is some problem there.
> > This would be nice to track down. What's running into it?
> llvm[3]: Building X86.td "fast" instruction selector implementation with tblgen
> warning:Multiple instructions match and one with no predicate came before one with a predicate!  name:VBROADCASTSSZr  predicate: (Subtarget->hasAVX512())
> 
> 
> .. unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4f32_MVT_v16f32_r(unsigned Op0, bool Op0IsKill) {
> ..  return fastEmitInst_r(X86::VBROADCASTSSZr, &X86::VR512RegClass, Op0, Op0IsKill);
> ..  if ((Subtarget->hasAVX512())) {
> ..    return fastEmitInst_r(X86::VBROADCASTSSZr, &X86::VR512RegClass, Op0, Op0IsKill);
> ..  }
> .. }
> 
> That function comes out the same way either or without these changes.
> 
That's... lovely.

Don't worry about it. I've looked at the .td files and it would need some work to fix it. It is a problem in the X86 backend, but until we can fix it we can't do anything about it.

Perhaps file a bug and leave a comment that this should be an error?

http://reviews.llvm.org/D6220