[PATCH] [X86] Refactor PMOV[SZ]Xrm to add missing AVX2 patterns.

Elena Demikhovsky elena.demikhovsky at intel.com
Thu Nov 13 05:29:07 PST 2014


Hi, In my opinion you have a lot of redundant patterns. And not each pattern is accompanied with test.
If you can't write a code that use the pattern - it should be removed.

As far as I know, we don't fold FP load to integer operation. Am I wrong?

================
Comment at: lib/Target/X86/X86InstrSSE.td:6168
@@ +6167,3 @@
+  def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
+            (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
+  def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
----------------
Why v32i8 ? How do you get it? If you have v8i8 it will be legalized to v8i32 or v8i16.
I think you have a lot of redundant patterns.

================
Comment at: lib/Target/X86/X86InstrSSE.td:6175
@@ +6174,3 @@
+  def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
+            (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
+  def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
----------------
How do we get this pattern? Why do we try v16i16 ->zext->v8i32?
I think that the only possible pattern is v8i16 ->zext->v8i32.

================
Comment at: lib/Target/X86/X86InstrSSE.td:6286
@@ +6285,3 @@
+            (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
+  def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
+            (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
----------------
How do we extend float to i32? I don't think that we need to fold FP load to integer operation.

http://reviews.llvm.org/D6125






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