[PATCH] Change order of tablegen generated fastisel instruction code to be based on instruction complexity

[Eric Christopher]

In general looks good. Couple of inline comments and fixing the bit that Bill pointed out would be nice.

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Comment at: /home/seurer/llvm/llvm-oneoff/utils/TableGen/FastISelEmitter.cpp:669
@@ -646,1 +668,3 @@
+                               "  predicate: " + PredicateCheck);
+                }
                 OS << "  if (" + PredicateCheck + ") {\n";
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seurer wrote:
> Should this PrintWarning be an PrintError or an assert?  The X86 target actually hits this at least once so perhaps there is some problem there.
This would be nice to track down. What's running into it?

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Comment at: /home/seurer/llvm/llvm-oneoff/utils/TableGen/FastISelEmitter.cpp:700
@@ +699,3 @@
+            }
+            // Return 0 if none of the predicates were satisfied and there
+            // was not one without a predicate.
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Too many negatives in this comment, could you reword please?

http://reviews.llvm.org/D6220