[PATCH] Masked Vector Load/Store Intrinsics

[hfinkel at anl.gov]

================
Comment at: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:1021
@@ +1020,3 @@
+                         MachineMemOperand::MOLoad,  HiMemVT.getStoreSize(),
+                         Alignment, MLD->getAAInfo(), MLD->getRanges());
+
----------------
delena wrote:
> hfinkel wrote:
> > This alignment is not right -- if the full load as alignment Alignment, then the upper half can have only half that.
> Usually alignment is not bigger than element size in this case.
> We started, for example, from
> %res = load i32 *%ptr, align 4
> and created a call to intrinsic
> %res.v = call <16 x i32> @llvm.masked.load(%ptr, %mask, undef, 4) - alignment is still 4 
> not we decided to split into two, alignment should remain the same.
> So, vectorizer can't create masked load for
> %res = load i32 *%ptr, align 64. Or I'm wrong?
> 
> Another question, what happens if user writes IR and specifies another alignment?
> %res.v = call <16 x i32> @llvm.masked.load(%ptr, %mask, undef, 64)
> Theoretically, if alignment is bigger than original size - splitting is wrong.
> I can spit alignment if alignment is equal to the original size.
> 
> Look at SplitVecRes_LOAD() - nobody splits alignment there.
> 
You're right, you only need to divide the alignment by 2 if it is larger than the size of the half vector. Otherwise, leave it alone.

The validity of the splitting is based on type legality, and should have nothing to do with the alignment.

> Look at SplitVecRes_LOAD() - nobody splits alignment there.

Sounds like a bug.

http://reviews.llvm.org/D6191