[PATCH] [AArch64] Inline memcpy() as a sequence of ldp-stp with 64-bit registers

[James Molloy]

> In this case it could ignore latency of ldp when it's followed by stp with same operands.

I don't think that's right. We're not magically going to make the stp less quick, we can just issue them back to back in the same cycle. Potentially a ScheduleHazardRecognizer might be the right thing here?

http://reviews.llvm.org/D6054