[llvm] r221693 - LLVM incorrectly folds xor into select

[Oliver Stannard]

Author: olista01
Date: Tue Nov 11 11:36:01 2014
New Revision: 221693

URL: http://llvm.org/viewvc/llvm-project?rev=221693&view=rev
Log:
LLVM incorrectly folds xor into select

LLVM replaces the SelectionDAG pattern (xor (set_cc cc x y) 1) with
(set_cc !cc x y), which is only correct when the xor has type i1.
Instead, we should check that the constant operand to the xor is all
ones.


Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/ARM/select_xform.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=221693&r1=221692&r2=221693&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Nov 11 11:36:01 2014
@@ -3826,7 +3826,8 @@ SDValue DAGCombiner::visitXOR(SDNode *N)
     return RXOR;
 
   // fold !(x cc y) -> (x !cc y)
-  if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
+  if (N1C && N1C->getAPIntValue().isAllOnesValue() &&
+      isSetCCEquivalent(N0, LHS, RHS, CC)) {
     bool isInt = LHS.getValueType().isInteger();
     ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
                                                isInt);

Modified: llvm/trunk/test/CodeGen/ARM/select_xform.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select_xform.ll?rev=221693&r1=221692&r2=221693&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/select_xform.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/select_xform.ll Tue Nov 11 11:36:01 2014
@@ -222,3 +222,20 @@ entry:
   %add = add i32 %conv, %c
   ret i32 %add
 }
+
+; Do not fold the xor into the select
+define i32 @t15(i32 %p1, i32 %p2, i32 %p3) {
+entry:
+; ARM: cmp            r0, #8
+; ARM: mov{{(le|gt)}} [[REG:r[0-9]+]], {{r[0-9]+}}
+; ARM: eor            r0, [[REG]], #1
+
+; T2: cmp       r0, #8
+; T2: it        [[CC:(le|gt)]]
+; T2: mov[[CC]] [[REG:r[0-9]+]], {{r[0-9]+}}
+; T2: eor       r0, [[REG:r[0-9]+]], #1
+  %cmp = icmp sgt i32 %p1, 8
+  %a = select i1 %cmp, i32 %p2, i32 %p3
+  %xor = xor i32 %a, 1
+  ret i32 %xor
+}