[llvm] r221686 - [mips] Add preliminary support for the MIPS II target.
Vasileios Kalintiris
Vasileios.Kalintiris at imgtec.com
Tue Nov 11 03:43:56 PST 2014
Author: vkalintiris
Date: Tue Nov 11 05:43:55 2014
New Revision: 221686
URL: http://llvm.org/viewvc/llvm-project?rev=221686&view=rev
Log:
[mips] Add preliminary support for the MIPS II target.
Summary:
This patch enables code generation for the MIPS II target. Pre-Mips32
targets don't have the MUL instruction, so we add the correspondent
pattern that uses the MULT/MFLO combination in order to retrieve the
product.
This is WIP as we don't support code generation for select nodes due to
the lack of conditional-move instructions.
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6150
Added:
llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
llvm/trunk/lib/Target/Mips/MipsSubtarget.h
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=221686&r1=221685&r2=221686&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Nov 11 05:43:55 2014
@@ -1653,6 +1653,12 @@ let AdditionalPredicates = [NotDSP] in {
(ADDiu GPR32:$src, imm:$imm)>;
}
+// Support multiplication for pre-Mips32 targets that don't have
+// the MUL instruction.
+def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),
+ (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,
+ ISA_MIPS1_NOT_32R6_64R6;
+
// SYNC
def : MipsPat<(MipsSync (i32 immz)),
(SYNC 0)>, ISA_MIPS2;
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=221686&r1=221685&r2=221686&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Tue Nov 11 05:43:55 2014
@@ -109,7 +109,7 @@ static std::string computeDataLayout(con
MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool little,
const MipsTargetMachine *_TM)
- : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
+ : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
ABI(MipsABIInfo::Unknown()), IsLittle(little), IsSingleFloat(false),
IsFPXX(false), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
@@ -126,13 +126,14 @@ MipsSubtarget::MipsSubtarget(const std::
PreviousInMips16Mode = InMips16Mode;
- // Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
- // MIPS-V. They have not been tested and currently exist for the integrated
+ if (MipsArchVersion == MipsDefault)
+ MipsArchVersion = Mips32;
+
+ // Don't even attempt to generate code for MIPS-I, MIPS-III and MIPS-V.
+ // They have not been tested and currently exist for the integrated
// assembler only.
if (MipsArchVersion == Mips1)
report_fatal_error("Code generation for MIPS-I is not implemented", false);
- if (MipsArchVersion == Mips2)
- report_fatal_error("Code generation for MIPS-II is not implemented", false);
if (MipsArchVersion == Mips3)
report_fatal_error("Code generation for MIPS-III is not implemented",
false);
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=221686&r1=221685&r2=221686&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Tue Nov 11 05:43:55 2014
@@ -37,6 +37,7 @@ class MipsSubtarget : public MipsGenSubt
virtual void anchor();
enum MipsArchEnum {
+ MipsDefault,
Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
Mips64r2, Mips64r6
};
Added: llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll?rev=221686&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll Tue Nov 11 05:43:55 2014
@@ -0,0 +1,181 @@
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=M2
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R1
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R2
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=32R6
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=M4
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=64R1-R2
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=64R1-R2
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=64R6
+
+define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
+entry:
+; ALL-LABEL: mul_i1:
+
+ ; M2: mult $4, $5
+ ; M2: mflo $[[T0:[0-9]+]]
+ ; M2: sll $[[T0]], $[[T0]], 31
+ ; M2: sra $2, $[[T0]], 31
+
+ ; 32R1-R2: mul $[[T0:[0-9]+]], $4, $5
+ ; 32R1-R2: sll $[[T0]], $[[T0]], 31
+ ; 32R1-R2: sra $2, $[[T0]], 31
+
+ ; 32R6: mul $[[T0:[0-9]+]], $4, $5
+ ; 32R6: sll $[[T0]], $[[T0]], 31
+ ; 32R6: sra $2, $[[T0]], 31
+
+ ; M4: mult $4, $5
+ ; M4: mflo $[[T0:[0-9]+]]
+ ; M4: sll $[[T0]], $[[T0]], 31
+ ; M4: sra $2, $[[T0]], 31
+
+ ; 64R1-R2: mul $[[T0:[0-9]+]], $4, $5
+ ; 64R1-R2: sll $[[T0]], $[[T0]], 31
+ ; 64R1-R2: sra $2, $[[T0]], 31
+
+ ; 64R6: mul $[[T0:[0-9]+]], $4, $5
+ ; 64R6: sll $[[T0]], $[[T0]], 31
+ ; 64R6: sra $2, $[[T0]], 31
+
+ %r = mul i1 %a, %b
+ ret i1 %r
+}
+
+define signext i8 @mul_i8(i8 signext %a, i8 signext %b) {
+entry:
+; ALL-LABEL: mul_i8:
+
+ ; M2: mult $4, $5
+ ; M2: mflo $[[T0:[0-9]+]]
+ ; M2: sll $[[T0]], $[[T0]], 24
+ ; M2: sra $2, $[[T0]], 24
+
+ ; 32R1: mul $[[T0:[0-9]+]], $4, $5
+ ; 32R1: sll $[[T0]], $[[T0]], 24
+ ; 32R1: sra $2, $[[T0]], 24
+
+ ; 32R2: mul $[[T0:[0-9]+]], $4, $5
+ ; 32R2: seb $2, $[[T0]]
+
+ ; 32R6: mul $[[T0:[0-9]+]], $4, $5
+ ; 32R6: seb $2, $[[T0]]
+
+ ; M4: mult $4, $5
+ ; M4: mflo $[[T0:[0-9]+]]
+ ; M4: sll $[[T0]], $[[T0]], 24
+ ; M4: sra $2, $[[T0]], 24
+
+ ; 64R1: mul $[[T0:[0-9]+]], $4, $5
+ ; 64R1: sll $[[T0]], $[[T0]], 24
+ ; 64R1: sra $2, $[[T0]], 24
+
+ ; 64R2: mul $[[T0:[0-9]+]], $4, $5
+ ; 64R2: seb $2, $[[T0]]
+
+ ; 64R6: mul $[[T0:[0-9]+]], $4, $5
+ ; 64R6: seb $2, $[[T0]]
+ %r = mul i8 %a, %b
+ ret i8 %r
+}
+
+define signext i16 @mul_i16(i16 signext %a, i16 signext %b) {
+entry:
+; ALL-LABEL: mul_i16:
+
+ ; M2: mult $4, $5
+ ; M2: mflo $[[T0:[0-9]+]]
+ ; M2: sll $[[T0]], $[[T0]], 16
+ ; M2: sra $2, $[[T0]], 16
+
+ ; 32R1: mul $[[T0:[0-9]+]], $4, $5
+ ; 32R1: sll $[[T0]], $[[T0]], 16
+ ; 32R1: sra $2, $[[T0]], 16
+
+ ; 32R2: mul $[[T0:[0-9]+]], $4, $5
+ ; 32R2: seh $2, $[[T0]]
+
+ ; 32R6: mul $[[T0:[0-9]+]], $4, $5
+ ; 32R6: seh $2, $[[T0]]
+
+ ; M4: mult $4, $5
+ ; M4: mflo $[[T0:[0-9]+]]
+ ; M4: sll $[[T0]], $[[T0]], 16
+ ; M4: sra $2, $[[T0]], 16
+
+ ; 64R1: mul $[[T0:[0-9]+]], $4, $5
+ ; 64R1: sll $[[T0]], $[[T0]], 16
+ ; 64R1: sra $2, $[[T0]], 16
+
+ ; 64R2: mul $[[T0:[0-9]+]], $4, $5
+ ; 64R2: seh $2, $[[T0]]
+
+ ; 64R6: mul $[[T0:[0-9]+]], $4, $5
+ ; 64R6: seh $2, $[[T0]]
+ %r = mul i16 %a, %b
+ ret i16 %r
+}
+
+define signext i32 @mul_i32(i32 signext %a, i32 signext %b) {
+entry:
+; ALL-LABEL: mul_i32:
+
+ ; M2: mult $4, $5
+ ; M2: mflo $2
+
+ ; 32R1-R2: mul $2, $4, $5
+ ; 32R6: mul $2, $4, $5
+
+ ; 64R1-R2: mul $2, $4, $5
+ ; 64R6: mul $2, $4, $5
+ %r = mul i32 %a, %b
+ ret i32 %r
+}
+
+define signext i64 @mul_i64(i64 signext %a, i64 signext %b) {
+entry:
+; ALL-LABEL: mul_i64:
+
+ ; M2: mult $4, $7
+ ; M2: mflo $[[T0:[0-9]+]]
+ ; M2: mult $5, $6
+ ; M2: mflo $[[T1:[0-9]+]]
+ ; M2: multu $5, $7
+ ; M2: mflo $3
+ ; M2: mfhi $4
+ ; M2: addu $[[T2:[0-9]+]], $4, $[[T1]]
+ ; M2: addu $2, $[[T2]], $[[T0]]
+
+ ; 32R1-R2: multu $5, $7
+ ; 32R1-R2: mflo $3
+ ; 32R1-R2: mfhi $[[T0:[0-9]+]]
+ ; 32R1-R2: mul $[[T1:[0-9]+]], $4, $7
+ ; 32R1-R2: mul $[[T2:[0-9]+]], $5, $6
+ ; 32R1-R2: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]]
+ ; 32R1-R2: addu $2, $[[T0]], $[[T1]]
+
+ ; 32R6: mul $[[T0:[0-9]+]], $5, $6
+ ; 32R6: muhu $[[T1:[0-9]+]], $5, $7
+ ; 32R6: addu $[[T0]], $[[T1]], $[[T0]]
+ ; 32R6: mul $[[T2:[0-9]+]], $4, $7
+ ; 32R6: addu $2, $[[T0]], $[[T2]]
+ ; 32R6: mul $3, $5, $7
+
+ ; M4: dmult $4, $5
+ ; M4: mflo $2
+
+ ; 64R1-R2: dmult $4, $5
+ ; 64R1-R2: mflo $2
+
+ ; 64R6: dmul $2, $4, $5
+
+ %r = mul i64 %a, %b
+ ret i64 %r
+}
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