[PATCH] Masked Vector Load/Store Intrinsics

[Elena Demikhovsky]

Hi anemet, hfinkel, rob.khasanov, resistor,

Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores.
Added SDNodes for masked operations and lowering patterns for X86 code generator.

Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch.

http://reviews.llvm.org/D6191

Files:
  include/llvm/Analysis/TargetTransformInfo.h
  include/llvm/CodeGen/ISDOpcodes.h
  include/llvm/CodeGen/SelectionDAG.h
  include/llvm/CodeGen/SelectionDAGNodes.h
  include/llvm/IR/IRBuilder.h
  include/llvm/IR/Intrinsics.h
  include/llvm/IR/Intrinsics.td
  include/llvm/Target/TargetSelectionDAG.td
  lib/Analysis/TargetTransformInfo.cpp
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  lib/CodeGen/SelectionDAG/LegalizeTypes.h
  lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
  lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  lib/IR/Function.cpp
  lib/IR/IRBuilder.cpp
  lib/IR/Verifier.cpp
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86InstrAVX512.td
  lib/Target/X86/X86InstrSSE.td
  lib/Target/X86/X86TargetTransformInfo.cpp
  lib/Transforms/Vectorize/LoopVectorize.cpp
  test/CodeGen/X86/masked_memop.ll
  test/Transforms/LoopVectorize/X86/mask1.ll
  test/Transforms/LoopVectorize/X86/mask2.ll
  test/Transforms/LoopVectorize/X86/mask3.ll
  test/Transforms/LoopVectorize/X86/mask4.ll
  utils/TableGen/CodeGenTarget.cpp
  utils/TableGen/IntrinsicEmitter.cpp
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