[PATCH] [PowerPC] Add vec_vsx_ld and vec_vsx_st intrinsics

[Bill Schmidt]

Hi hfinkel, seurer, willschm,

This patch enables the vec_vsx_ld and vec_vsx_st intrinsics for PowerPC, which provide programmer access to the lxvd2x, lxvw4x, stxvd2x, and stxvw4x instructions.

New LLVM intrinsics are provided to represent these four instructions in IntrinsicsPowerPC.td.  These are patterned after the similar intrinsics for lvx and stvx (Altivec).  In PPCInstrVSX.td, these intrinsics are tied to the code gen patterns, with additional patterns to allow plain vanilla loads and stores to still generate these instructions.

At -O1 and higher the intrinsics are immediately converted to loads and stores in InstCombineCalls.cpp.  This will open up more optimization opportunities while still allowing the correct instructions to be generated.  (Similar code exists for aligned Altivec loads and stores.)

The new intrinsics are added to the code that checks for consecutive loads and stores in PPCISelLowering.cpp, as well as to PPCTargetLowering::getTgtMemIntrinsic().

There's a new test to verify the correct instructions are generated.  The loads and stores tend to be reordered, so the test just counts their number.  It runs at -O2, as it's not very effective to test this
at -O0, when many unnecessary loads and stores are generated.

I ended up having to modify vsx-fma-m.ll.  It turns out this test case is slightly unreliable, but I don't know a good way to prevent problems with it.  The xvmaddmdp instructions read and write the same
register, which is one of the multiplicands.  Commutativity allows either to be chosen.  If the FMAs are reordered differently than expected by the test, the register assignment can be different as a result.  Hopefully this doesn't change often, but my patch appears to have been sufficient to trigger a different schedule for some unknown reason.  Ideas welcome of a better way to deal with this.

There is a companion patch for Clang, to be reviewed separately.

http://reviews.llvm.org/D6143

Files:
  include/llvm/IR/IntrinsicsPowerPC.td
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCInstrVSX.td
  lib/Transforms/InstCombine/InstCombineCalls.cpp
  test/CodeGen/PowerPC/vsx-fma-m.ll
  test/CodeGen/PowerPC/vsx-ldst.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D6143.15830.patch
Type: text/x-patch
Size: 10039 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20141105/615b523b/attachment.bin>