[llvm] r220779 - [AVX512] Removed special case for cmp instructions in getVectorMaskingNode. Now cmp intrinsics lower as other intrinsics through VSELECT, and then VSELECT tranforms to AND in PerformSELECTCombine.

[NAKAMURA Takumi]

I reverted r220779 to satisfy tests since r221028. But r221028 was
reverted a few hours after.

I guess r220779 could be relanded. Could you reapply r220779 ? Or I can.

Excuse me for inconvenience.

2014-10-29 1:17 GMT+09:00 Robert Khasanov <rob.khasanov at gmail.com>:
> Author: rkhasanov
> Date: Tue Oct 28 11:17:14 2014
> New Revision: 220779
>
> URL: http://llvm.org/viewvc/llvm-project?rev=220779&view=rev
> Log:
> [AVX512] Removed special case for cmp instructions in getVectorMaskingNode. Now cmp intrinsics lower as other intrinsics through VSELECT, and then VSELECT tranforms to AND in PerformSELECTCombine.
> No functional change.
>
> Modified:
>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=220779&r1=220778&r2=220779&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Oct 28 11:17:14 2014
> @@ -16158,8 +16158,7 @@ static SDValue getTargetVShiftNode(unsig
>    return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
>  }
>
> -/// \brief Return (and \p Op, \p Mask) for compare instructions or
> -/// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
> +/// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
>  /// necessary casting for \p Mask when lowering masking intrinsics.
>  static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
>                                      SDValue PreservedSrc, SelectionDAG &DAG) {
> @@ -16180,16 +16179,6 @@ static SDValue getVectorMaskingNode(SDVa
>      SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
>                                DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
>                                DAG.getIntPtrConstant(0));
> -
> -    switch (Op.getOpcode()) {
> -      default: break;
> -      case X86ISD::PCMPEQM:
> -      case X86ISD::PCMPGTM:
> -      case X86ISD::CMPM:
> -      case X86ISD::CMPMU:
> -        return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
> -    }
> -
>      return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
>  }
>
> @@ -16264,9 +16253,9 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S
>        //             (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
>        // (i8 (bitcast
>        //   (v8i1 (insert_subvector undef,
> -      //           (v2i1 (and (PCMPEQM %a, %b),
> -      //                      (extract_subvector
> -      //                         (v8i1 (bitcast %mask)), 0))), 0))))
> +      //           (v2i1 (vselect (extract_subvector
> +      //                            (v8i1 (bitcast %mask)), 0),
> +      //                          (PCMPEQM %a, %b), 0))))))
>        EVT VT = Op.getOperand(1).getValueType();
>        EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
>                                      VT.getVectorNumElements());
>
>
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