[llvm] r221308 - [AArch64] Use the correct register class for ORR.

[Juergen Ributzka]

Author: ributzka
Date: Tue Nov  4 16:20:07 2014
New Revision: 221308

URL: http://llvm.org/viewvc/llvm-project?rev=221308&view=rev
Log:
[AArch64] Use the correct register class for ORR.

While fixing up the register classes in the machine combiner in a previous
commit I missed one.

This fixes the last one and adds a test case.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
    llvm/trunk/test/CodeGen/AArch64/madd-combiner.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=221308&r1=221307&r2=221308&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Tue Nov  4 16:20:07 2014
@@ -2805,7 +2805,7 @@ void AArch64InstrInfo::genAlternativeCod
       RC = &AArch64::GPR32RegClass;
     } else {
       OrrOpc = AArch64::ORRXri;
-      OrrRC = &AArch64::GPR64RegClass;
+      OrrRC = &AArch64::GPR64spRegClass;
       BitSize = 64;
       ZeroReg = AArch64::XZR;
       Opc = AArch64::MADDXrrr;

Modified: llvm/trunk/test/CodeGen/AArch64/madd-combiner.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/madd-combiner.ll?rev=221308&r1=221307&r2=221308&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/madd-combiner.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/madd-combiner.ll Tue Nov  4 16:20:07 2014
@@ -1,4 +1,5 @@
-; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin            -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs < %s | FileCheck %s
 
 ; Test that we use the correct register class.
 define i32 @mul_add_imm(i32 %a, i32 %b) {
@@ -18,3 +19,19 @@ define i32 @mul_sub_imm1(i32 %a, i32 %b)
   %2 = sub i32 4, %1
   ret i32 %2
 }
+
+; bugpoint reduced test case. This only tests that we pass the MI verifier.
+define void @mul_add_imm2() {
+entry:
+  br label %for.body
+for.body:
+  br i1 undef, label %for.body, label %for.body8
+for.body8:
+  %0 = mul i64 undef, -3
+  %mul1971 = add i64 %0, -3
+  %cmp7 = icmp slt i64 %mul1971, 1390451930000
+  br i1 %cmp7, label %for.body8, label %for.end20
+for.end20:
+  ret void
+}
+