[PATCH] Support REG_SEQUENCE in tablegen.
Matt Arsenault
Matthew.Arsenault at amd.com
Sat Nov 1 21:27:13 PDT 2014
The problem is mostly that variadic output instruction
aren't handled, so it is rejected for having an inconsistent
number of operands, and then the right number of operands
isn't emitted.
I'm not particularly confident in custom typechecking for the
operands since it seems more complicated than it should be.
http://reviews.llvm.org/D6075
Files:
include/llvm/Target/Target.td
lib/Target/R600/SIInstructions.td
utils/TableGen/CodeGenDAGPatterns.cpp
utils/TableGen/DAGISelMatcherGen.cpp
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