[llvm] r221054 - [mips] Remove MipsCC::CCInfo. NFC.
Daniel Sanders
daniel.sanders at imgtec.com
Sat Nov 1 11:13:52 PDT 2014
Author: dsanders
Date: Sat Nov 1 13:13:52 2014
New Revision: 221054
URL: http://llvm.org/viewvc/llvm-project?rev=221054&view=rev
Log:
[mips] Remove MipsCC::CCInfo. NFC.
Summary:
It's now passed in as an argument to functions that need it. Eventually
this argument will be replaced by the 'this' pointer for a MipsCCState
object.
Depends on D5966
Reviewers: vmedic
Reviewed By: vmedic
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5967
Modified:
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsISelLowering.h
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=221054&r1=221053&r2=221054&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Sat Nov 1 13:13:52 2014
@@ -2550,9 +2550,8 @@ MipsTargetLowering::LowerCall(TargetLowe
*DAG.getContext());
MipsCC MipsCCInfo(CallConv, Subtarget, CCInfo);
- MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
- Subtarget.abiUsesSoftFloat(),
- Callee.getNode(), CLI.getArgs());
+ MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, Subtarget.abiUsesSoftFloat(),
+ Callee.getNode(), CLI.getArgs(), CCInfo);
// Get a count of how many bytes are to be pushed on the stack.
unsigned NextStackOffset = CCInfo.getNextStackOffset();
@@ -2837,7 +2836,7 @@ MipsTargetLowering::LowerFormalArguments
DAG.getMachineFunction().getFunction()->arg_begin();
bool UseSoftFloat = Subtarget.abiUsesSoftFloat();
- MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg);
+ MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg, CCInfo);
MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
MipsCCInfo.hasByValArg());
@@ -2943,7 +2942,7 @@ MipsTargetLowering::LowerFormalArguments
}
if (IsVarArg)
- writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG);
+ writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG, CCInfo);
// All stores are grouped in one node to allow the matching between
// the size of Ins and InVals. This only happens when on varg functions
@@ -3532,16 +3531,15 @@ MipsTargetLowering::MipsCC::getSpecialCa
MipsTargetLowering::MipsCC::MipsCC(CallingConv::ID CC,
const MipsSubtarget &Subtarget_,
CCState &Info)
- : CCInfo(Info), CallConv(CC), Subtarget(Subtarget_) {
+ : CallConv(CC), Subtarget(Subtarget_) {
// Pre-allocate reserved argument area.
- CCInfo.AllocateStack(reservedArgArea(), 1);
+ Info.AllocateStack(reservedArgArea(), 1);
}
-
-void MipsTargetLowering::MipsCC::
-analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
- bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode,
- std::vector<ArgListEntry> &FuncArgs) {
+void MipsTargetLowering::MipsCC::analyzeCallOperands(
+ const SmallVectorImpl<ISD::OutputArg> &Args, bool IsVarArg,
+ bool IsSoftFloat, const SDNode *CallNode,
+ std::vector<ArgListEntry> &FuncArgs, CCState &State) {
MipsCC::SpecialCallingConvType SpecialCallingConv =
getSpecialCallingConv(CallNode);
assert((CallConv != CallingConv::Fast || !IsVarArg) &&
@@ -3559,16 +3557,16 @@ analyzeCallOperands(const SmallVectorImp
bool R;
if (ArgFlags.isByVal()) {
- handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
+ handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, State);
continue;
}
if (IsVarArg && !Args[I].IsFixed)
- R = CC_Mips_VarArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
+ R = CC_Mips_VarArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, State);
else {
MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode,
IsSoftFloat);
- R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo);
+ R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, State);
}
if (R) {
@@ -3581,9 +3579,9 @@ analyzeCallOperands(const SmallVectorImp
}
}
-void MipsTargetLowering::MipsCC::
-analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args,
- bool IsSoftFloat, Function::const_arg_iterator FuncArg) {
+void MipsTargetLowering::MipsCC::analyzeFormalArguments(
+ const SmallVectorImpl<ISD::InputArg> &Args, bool IsSoftFloat,
+ Function::const_arg_iterator FuncArg, CCState &State) {
unsigned NumArgs = Args.size();
unsigned CurArgIdx = 0;
@@ -3594,13 +3592,13 @@ analyzeFormalArguments(const SmallVector
CurArgIdx = Args[I].OrigArgIndex;
if (ArgFlags.isByVal()) {
- handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
+ handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, State);
continue;
}
MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), nullptr, IsSoftFloat);
- if (!CC_Mips_FixedArg(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo))
+ if (!CC_Mips_FixedArg(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, State))
continue;
#ifndef NDEBUG
@@ -3614,7 +3612,8 @@ analyzeFormalArguments(const SmallVector
void MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
MVT LocVT,
CCValAssign::LocInfo LocInfo,
- ISD::ArgFlagsTy ArgFlags) {
+ ISD::ArgFlagsTy ArgFlags,
+ CCState &State) {
assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
struct ByValArgInfo ByVal;
@@ -3625,13 +3624,13 @@ void MipsTargetLowering::MipsCC::handleB
RegSizeInBytes * 2);
if (useRegsForByval())
- allocateRegs(ByVal, ByValSize, Align);
+ allocateRegs(ByVal, ByValSize, Align, State);
// Allocate space on caller's stack.
ByVal.Address =
- CCInfo.AllocateStack(ByValSize - RegSizeInBytes * ByVal.NumRegs, Align);
- CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
- LocInfo));
+ State.AllocateStack(ByValSize - RegSizeInBytes * ByVal.NumRegs, Align);
+ State.addLoc(
+ CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, LocInfo));
ByValArgs.push_back(ByVal);
}
@@ -3651,7 +3650,7 @@ const MCPhysReg *MipsTargetLowering::Mip
void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
unsigned ByValSize,
- unsigned Align) {
+ unsigned Align, CCState &State) {
unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
const ArrayRef<MCPhysReg> IntArgRegs = intArgRegs();
const MCPhysReg *ShadowRegs = shadowRegs();
@@ -3660,18 +3659,18 @@ void MipsTargetLowering::MipsCC::allocat
"RegSizeInBytes.");
ByVal.FirstIdx =
- CCInfo.getFirstUnallocated(IntArgRegs.data(), IntArgRegs.size());
+ State.getFirstUnallocated(IntArgRegs.data(), IntArgRegs.size());
// If Align > RegSizeInBytes, the first arg register must be even.
if ((Align > RegSizeInBytes) && (ByVal.FirstIdx % 2)) {
- CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
+ State.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
++ByVal.FirstIdx;
}
// Mark the registers allocated.
for (unsigned I = ByVal.FirstIdx; ByValSize && (I < IntArgRegs.size());
ByValSize -= RegSizeInBytes, ++I, ++ByVal.NumRegs)
- CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
+ State.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
}
MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
@@ -3834,10 +3833,10 @@ passByValArg(SDValue Chain, SDLoc DL,
void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
const MipsCC &CC, SDValue Chain,
- SDLoc DL, SelectionDAG &DAG) const {
+ SDLoc DL, SelectionDAG &DAG,
+ CCState &State) const {
const ArrayRef<MCPhysReg> ArgRegs = CC.intArgRegs();
- const CCState &CCInfo = CC.getCCInfo();
- unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs.data(), ArgRegs.size());
+ unsigned Idx = State.getFirstUnallocated(ArgRegs.data(), ArgRegs.size());
unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
const TargetRegisterClass *RC = getRegClassFor(RegTy);
@@ -3850,7 +3849,7 @@ void MipsTargetLowering::writeVarArgRegs
if (ArgRegs.size() == Idx)
VaArgOffset =
- RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSizeInBytes);
+ RoundUpToAlignment(State.getNextStackOffset(), RegSizeInBytes);
else
VaArgOffset = (int)CC.reservedArgArea() -
(int)(RegSizeInBytes * (ArgRegs.size() - Idx));
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=221054&r1=221053&r2=221054&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Sat Nov 1 13:13:52 2014
@@ -362,12 +362,12 @@ namespace llvm {
void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
bool IsVarArg, bool IsSoftFloat,
const SDNode *CallNode,
- std::vector<ArgListEntry> &FuncArgs);
+ std::vector<ArgListEntry> &FuncArgs,
+ CCState &State);
void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
bool IsSoftFloat,
- Function::const_arg_iterator FuncArg);
-
- const CCState &getCCInfo() const { return CCInfo; }
+ Function::const_arg_iterator FuncArg,
+ CCState &State);
/// hasByValArg - Returns true if function has byval arguments.
bool hasByValArg() const { return !ByValArgs.empty(); }
@@ -386,7 +386,7 @@ namespace llvm {
private:
void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo,
- ISD::ArgFlagsTy ArgFlags);
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
/// useRegsForByval - Returns true if the calling convention allows the
/// use of registers to pass byval arguments.
@@ -394,8 +394,8 @@ namespace llvm {
const MCPhysReg *shadowRegs() const;
- void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
- unsigned Align);
+ void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, unsigned Align,
+ CCState &State);
/// Return the type of the register which is used to pass an argument or
/// return a value. This function returns f64 if the argument is an i64
@@ -410,7 +410,6 @@ namespace llvm {
SpecialCallingConvType getSpecialCallingConv(const SDNode *Callee) const;
- CCState &CCInfo;
CallingConv::ID CallConv;
const MipsSubtarget &Subtarget;
SmallVector<ByValArgInfo, 2> ByValArgs;
@@ -504,7 +503,8 @@ namespace llvm {
/// to the stack. Also create a stack frame object for the first variable
/// argument.
void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
- SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
+ SDValue Chain, SDLoc DL, SelectionDAG &DAG,
+ CCState &State) const;
SDValue
LowerFormalArguments(SDValue Chain,
More information about the llvm-commits
mailing list