[llvm] r220945 - PR20557: Fix the bug that bogus cpu parameter crashes llc on AArch64 backend.
Hao Liu
Hao.Liu at arm.com
Thu Oct 30 19:35:34 PDT 2014
Author: haoliu
Date: Thu Oct 30 21:35:34 2014
New Revision: 220945
URL: http://llvm.org/viewvc/llvm-project?rev=220945&view=rev
Log:
PR20557: Fix the bug that bogus cpu parameter crashes llc on AArch64 backend.
Initial patch by Oleg Ranevskyy.
Added:
llvm/trunk/test/CodeGen/AArch64/legalize-bug-bogus-cpu.ll
Modified:
llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
Modified: llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=220945&r1=220944&r2=220945&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp Thu Oct 30 21:35:34 2014
@@ -1200,8 +1200,12 @@ void TargetLoweringBase::computeRegister
TransformToType[i] = MVT::Other;
if (PreferredAction == TypeScalarizeVector)
ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
- else
+ else if (PreferredAction == TypeSplitVector)
ValueTypeActions.setTypeAction(VT, TypeSplitVector);
+ else
+ // Set type action according to the number of elements.
+ ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
+ : TypeSplitVector);
} else {
TransformToType[i] = NVT;
ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Added: llvm/trunk/test/CodeGen/AArch64/legalize-bug-bogus-cpu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/legalize-bug-bogus-cpu.ll?rev=220945&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/legalize-bug-bogus-cpu.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/legalize-bug-bogus-cpu.ll Thu Oct 30 21:35:34 2014
@@ -0,0 +1,8 @@
+; RUN: llc -march=aarch64 -mcpu=bogus -o - %s
+
+; Fix the bug in PR20557. Set mcpu to a bogus name, llc will crash in type
+; legalization.
+define <4 x float> @fneg4(<4 x float> %x) {
+ %sub = fsub <4 x float> zeroinitializer, %x
+ ret <4 x float> %sub
+}
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