[llvm] r220477 - [mips][microMIPS] Implement ADDIUR1SP instruction
Zoran Jovanovic
zoran.jovanovic at imgtec.com
Thu Oct 23 04:14:00 PDT 2014
Author: zjovanovic
Date: Thu Oct 23 06:13:59 2014
New Revision: 220477
URL: http://llvm.org/viewvc/llvm-project?rev=220477&view=rev
Log:
[mips][microMIPS] Implement ADDIUR1SP instruction
Differential Revision: http://reviews.llvm.org/D5153
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s
llvm/trunk/test/MC/Mips/micromips-invalid.s
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=220477&r1=220476&r2=220477&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Thu Oct 23 06:13:59 2014
@@ -1187,6 +1187,16 @@ bool MipsAsmParser::processInstruction(M
((Imm % 4 == 0) && Imm < 28 && Imm > 0)))
return Error(IDLoc, "immediate operand value out of range");
break;
+ case Mips::ADDIUR1SP_MM:
+ Opnd = Inst.getOperand(1);
+ if (!Opnd.isImm())
+ return Error(IDLoc, "expected immediate operand kind");
+ Imm = Opnd.getImm();
+ if (OffsetToAlignment(Imm, 4LL))
+ return Error(IDLoc, "misaligned immediate operand value");
+ if (Imm < 0 || Imm > 255)
+ return Error(IDLoc, "immediate operand value out of range");
+ break;
}
}
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp?rev=220477&r1=220476&r2=220477&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Thu Oct 23 06:13:59 2014
@@ -378,6 +378,20 @@ getSImm3Lsa2Value(const MCInst &MI, unsi
}
unsigned MipsMCCodeEmitter::
+getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+
+ const MCOperand &MO = MI.getOperand(OpNo);
+ if (MO.isImm()) {
+ unsigned Value = MO.getImm();
+ return Value >> 2;
+ }
+
+ return 0;
+}
+
+unsigned MipsMCCodeEmitter::
getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h?rev=220477&r1=220476&r2=220477&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h Thu Oct 23 06:13:59 2014
@@ -84,6 +84,10 @@ public:
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+ unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
// getSImm9AddiuspValue - Return binary encoding of the microMIPS addiusp
// instruction immediate operand.
unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td?rev=220477&r1=220476&r2=220477&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td Thu Oct 23 06:13:59 2014
@@ -170,6 +170,18 @@ class JRADDIUSP_FM_MM16<bits<5> op> {
let Inst{4-0} = imm;
}
+class ADDIUR1SP_FM_MM16 {
+ bits<3> rd;
+ bits<6> imm;
+
+ bits<16> Inst;
+
+ let Inst{15-10} = 0x1b;
+ let Inst{9-7} = rd;
+ let Inst{6-1} = imm;
+ let Inst{0} = 1;
+}
+
//===----------------------------------------------------------------------===//
// MicroMIPS 32-bit Instruction Formats
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=220477&r1=220476&r2=220477&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Thu Oct 23 06:13:59 2014
@@ -11,6 +11,10 @@ def uimm5_lsl2 : Operand<OtherVT> {
let EncoderMethod = "getUImm5Lsl2Encoding";
}
+def uimm6_lsl2 : Operand<i32> {
+ let EncoderMethod = "getUImm6Lsl2Encoding";
+}
+
def simm9_addiusp : Operand<i32> {
let EncoderMethod = "getSImm9AddiuspValue";
}
@@ -149,6 +153,10 @@ class AddImmUS5<string opstr, RegisterOp
let isCommutable = 1;
}
+class AddImmUR1SP<string opstr, RegisterOperand RO> :
+ MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
+ !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
+
class AddImmUSP<string opstr> :
MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
!strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
@@ -256,6 +264,7 @@ def SLL16_MM : ShiftIMM16<"sll16", uimm3
immZExt2Shift, II_SLL>, SHIFT_FM_MM16<0>;
def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, srl,
immZExt2Shift, II_SRL>, SHIFT_FM_MM16<1>;
+def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
Modified: llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s?rev=220477&r1=220476&r2=220477&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s Thu Oct 23 06:13:59 2014
@@ -19,6 +19,7 @@
# CHECK-EL: srl16 $4, $17, 6 # encoding: [0x1d,0x26]
# CHECK-EL: li16 $3, -1 # encoding: [0xff,0xed]
# CHECK-EL: li16 $3, 126 # encoding: [0xfe,0xed]
+# CHECK-EL: addiur1sp $7, 4 # encoding: [0x83,0x6f]
# CHECK-EL: addiur2 $6, $7, -1 # encoding: [0x7e,0x6f]
# CHECK-EL: addiur2 $6, $7, 12 # encoding: [0x76,0x6f]
# CHECK-EL: addius5 $7, -2 # encoding: [0xfc,0x4c]
@@ -47,6 +48,7 @@
# CHECK-EB: srl16 $4, $17, 6 # encoding: [0x26,0x1d]
# CHECK-EB: li16 $3, -1 # encoding: [0xed,0xff]
# CHECK-EB: li16 $3, 126 # encoding: [0xed,0xfe]
+# CHECK-EB: addiur1sp $7, 4 # encoding: [0x6f,0x83]
# CHECK-EB: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e]
# CHECK-EB: addiur2 $6, $7, 12 # encoding: [0x6f,0x76]
# CHECK-EB: addius5 $7, -2 # encoding: [0x4c,0xfc]
@@ -73,6 +75,7 @@
srl16 $4, $17, 6
li16 $3, -1
li16 $3, 126
+ addiur1sp $7, 4
addiur2 $6, $7, -1
addiur2 $6, $7, 12
addius5 $7, -2
Modified: llvm/trunk/test/MC/Mips/micromips-invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-invalid.s?rev=220477&r1=220476&r2=220477&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-invalid.s Thu Oct 23 06:13:59 2014
@@ -1,6 +1,9 @@
# RUN: not llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips 2>%t1
# RUN: FileCheck %s < %t1
+ addiur1sp $7, 260 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+ addiur1sp $7, 241 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: misaligned immediate operand value
+ addiur1sp $8, 240 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
addius5 $7, 9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
addu16 $6, $14, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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