[llvm] r220393 - [Hexagon] Adding basic disassembler.
Rafael Avila de Espindola
rafael.espindola at gmail.com
Wed Oct 22 10:43:14 PDT 2014
Thanks!
Sent from my iPhone
> On Oct 22, 2014, at 12:49, Colin LeMahieu <colinl at codeaurora.org> wrote:
>
> Author: colinl
> Date: Wed Oct 22 11:49:14 2014
> New Revision: 220393
>
> URL: http://llvm.org/viewvc/llvm-project?rev=220393&view=rev
> Log:
> [Hexagon] Adding basic disassembler.
> Marking all instructions as CodeGenOnly since encoding bits are not set yet.
> http://reviews.llvm.org/D5829?vs=on&id=15023&whitespace=ignore-all#toc
>
> Added:
> llvm/trunk/lib/Target/Hexagon/Disassembler/
> llvm/trunk/lib/Target/Hexagon/Disassembler/CMakeLists.txt
> llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
> llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt
> llvm/trunk/lib/Target/Hexagon/Disassembler/Makefile
> Modified:
> llvm/trunk/lib/Target/Hexagon/CMakeLists.txt
> llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td
> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
> llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
> llvm/trunk/lib/Target/Hexagon/Makefile
>
> Modified: llvm/trunk/lib/Target/Hexagon/CMakeLists.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/CMakeLists.txt?rev=220393&r1=220392&r2=220393&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/CMakeLists.txt (original)
> +++ llvm/trunk/lib/Target/Hexagon/CMakeLists.txt Wed Oct 22 11:49:14 2014
> @@ -1,8 +1,9 @@
> -set(LLVM_TARGET_DEFINITIONS Hexagon.td)
> -
> -tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
> -tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
> -tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
> +set(LLVM_TARGET_DEFINITIONS Hexagon.td)
> +
> +tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler)
> +tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
> +tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
> +tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
> tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
> tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
> tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
> @@ -38,7 +39,8 @@ add_llvm_target(HexagonCodeGen
> HexagonCopyToCombine.cpp
> )
>
> -add_subdirectory(TargetInfo)
> -add_subdirectory(InstPrinter)
> -add_subdirectory(MCTargetDesc)
> -
> +add_subdirectory(TargetInfo)
> +add_subdirectory(InstPrinter)
> +add_subdirectory(MCTargetDesc)
> +add_subdirectory(Disassembler)
> +
>
> Added: llvm/trunk/lib/Target/Hexagon/Disassembler/CMakeLists.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/CMakeLists.txt?rev=220393&view=auto
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/Disassembler/CMakeLists.txt (added)
> +++ llvm/trunk/lib/Target/Hexagon/Disassembler/CMakeLists.txt Wed Oct 22 11:49:14 2014
> @@ -0,0 +1,3 @@
> +add_llvm_library(LLVMHexagonDisassembler
> + HexagonDisassembler.cpp
> + )
>
> Added: llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp?rev=220393&view=auto
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp (added)
> +++ llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp Wed Oct 22 11:49:14 2014
> @@ -0,0 +1,131 @@
> +//===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//
> +//
> +// The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +#include "MCTargetDesc/HexagonBaseInfo.h"
> +#include "MCTargetDesc/HexagonMCTargetDesc.h"
> +
> +#include "llvm/MC/MCContext.h"
> +#include "llvm/MC/MCDisassembler.h"
> +#include "llvm/MC/MCExpr.h"
> +#include "llvm/MC/MCFixedLenDisassembler.h"
> +#include "llvm/MC/MCInst.h"
> +#include "llvm/MC/MCInstrDesc.h"
> +#include "llvm/MC/MCSubtargetInfo.h"
> +#include "llvm/Support/Debug.h"
> +#include "llvm/Support/ErrorHandling.h"
> +#include "llvm/Support/LEB128.h"
> +#include "llvm/Support/MemoryObject.h"
> +#include "llvm/Support/raw_ostream.h"
> +#include "llvm/Support/TargetRegistry.h"
> +#include "llvm/Support/Endian.h"
> +
> +#include <vector>
> +#include <array>
> +
> +using namespace llvm;
> +
> +#define DEBUG_TYPE "hexagon-disassembler"
> +
> +using DecodeStatus = MCDisassembler::DecodeStatus;
> +
> +namespace {
> +/// \brief Hexagon disassembler for all Hexagon platforms.
> +class HexagonDisassembler : public MCDisassembler {
> +public:
> + HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx)
> + : MCDisassembler(STI, Ctx) {}
> +
> + DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
> + MemoryObject const ®ion, uint64_t address,
> + raw_ostream &vStream, raw_ostream &cStream) const override;
> +};
> +}
> +
> +static const uint16_t IntRegDecoderTable[] = {
> + Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
> + Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
> + Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
> + Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
> + Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
> + Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
> + Hexagon::R30, Hexagon::R31};
> +
> +static const uint16_t DoubleRegDecoderTable[] = {
> + Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
> + Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
> + Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
> + Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
> +
> +static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
> + Hexagon::P2, Hexagon::P3};
> +
> +static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
> + uint64_t /*Address*/,
> + void const *Decoder) {
> + if (RegNo > 31)
> + return MCDisassembler::Fail;
> +
> + unsigned Register = IntRegDecoderTable[RegNo];
> + Inst.addOperand(MCOperand::CreateReg(Register));
> + return MCDisassembler::Success;
> +}
> +
> +static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
> + uint64_t /*Address*/,
> + void const *Decoder) {
> + if (RegNo > 15)
> + return MCDisassembler::Fail;
> +
> + unsigned Register = DoubleRegDecoderTable[RegNo];
> + Inst.addOperand(MCOperand::CreateReg(Register));
> + return MCDisassembler::Success;
> +}
> +
> +static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
> + uint64_t /*Address*/,
> + void const *Decoder) {
> + if (RegNo > 3)
> + return MCDisassembler::Fail;
> +
> + unsigned Register = PredRegDecoderTable[RegNo];
> + Inst.addOperand(MCOperand::CreateReg(Register));
> + return MCDisassembler::Success;
> +}
> +
> +#include "HexagonGenDisassemblerTables.inc"
> +
> +static MCDisassembler *createHexagonDisassembler(Target const &T,
> + MCSubtargetInfo const &STI,
> + MCContext &Ctx) {
> + return new HexagonDisassembler(STI, Ctx);
> +}
> +
> +extern "C" void LLVMInitializeHexagonDisassembler() {
> + TargetRegistry::RegisterMCDisassembler(TheHexagonTarget,
> + createHexagonDisassembler);
> +}
> +
> +DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
> + MemoryObject const &Region,
> + uint64_t Address,
> + raw_ostream &os,
> + raw_ostream &cs) const {
> + std::array<uint8_t, 4> Bytes;
> + Size = 4;
> + if (Region.readBytes(Address, Bytes.size(), Bytes.data()) == -1) {
> + return MCDisassembler::Fail;
> + }
> + uint32_t insn =
> + llvm::support::endian::read<uint32_t, llvm::support::little,
> + llvm::support::unaligned>(Bytes.data());
> +
> + // Remove parse bits.
> + insn &= ~static_cast<uint32_t>(HexagonII::InstParseBits::INST_PARSE_MASK);
> + return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);
> +}
>
> Added: llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt?rev=220393&view=auto
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt (added)
> +++ llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt Wed Oct 22 11:49:14 2014
> @@ -0,0 +1,23 @@
> +;===-- ./lib/Target/Hexagon/Disassembler/LLVMBuild.txt ---------*- Conf -*--===;
> +;
> +; The LLVM Compiler Infrastructure
> +;
> +; This file is distributed under the University of Illinois Open Source
> +; License. See LICENSE.TXT for details.
> +;
> +;===------------------------------------------------------------------------===;
> +;
> +; This is an LLVMBuild description file for the components in this subdirectory.
> +;
> +; For more information on the LLVMBuild system, please see:
> +;
> +; http://llvm.org/docs/LLVMBuild.html
> +;
> +;===------------------------------------------------------------------------===;
> +
> +[component_0]
> +type = Library
> +name = HexagonDisassembler
> +parent = Hexagon
> +required_libraries = HexagonDesc MCDisassembler HexagonInfo Support
> +add_to_library_groups = Hexagon
>
> Added: llvm/trunk/lib/Target/Hexagon/Disassembler/Makefile
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/Makefile?rev=220393&view=auto
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/Disassembler/Makefile (added)
> +++ llvm/trunk/lib/Target/Hexagon/Disassembler/Makefile Wed Oct 22 11:49:14 2014
> @@ -0,0 +1,16 @@
> +##===-- lib/Target/Hexagon/Disassembler/Makefile -----------*- Makefile -*-===##
> +#
> +# The LLVM Compiler Infrastructure
> +#
> +# This file is distributed under the University of Illinois Open Source
> +# License. See LICENSE.TXT for details.
> +#
> +##===----------------------------------------------------------------------===##
> +
> +LEVEL = ../../../..
> +LIBRARYNAME = LLVMHexagonDisassembler
> +
> +# Hack: we need to include 'main' target directory to grab private headers
> +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
> +
> +include $(LEVEL)/Makefile.common
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td?rev=220393&r1=220392&r2=220393&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td Wed Oct 22 11:49:14 2014
> @@ -92,12 +92,18 @@ class InstHexagon<dag outs, dag ins, str
> let AsmString = asmstr;
> let Pattern = pattern;
> let Constraints = cstr;
> - let Itinerary = itin;
> - let Size = 4;
> -
> - // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
> -
> - // Instruction type according to the ISA.
> + let Itinerary = itin;
> + let Size = 4;
> +
> + // SoftFail is a field the disassembler can use to provide a way for
> + // instructions to not match without killing the whole decode process. It is
> + // mainly used for ARM, but Tablegen expects this field to exist or it fails
> + // to build the decode table.
> + field bits<32> SoftFail = 0;
> +
> + // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
> +
> + // Instruction type according to the ISA.
> IType Type = type;
> let TSFlags{4-0} = Type.Value;
>
> @@ -186,6 +192,7 @@ class InstHexagon<dag outs, dag ins, str
> "");
> let PNewValue = !if(isPredicatedNew, "new", "");
> let NValueST = !if(isNVStore, "true", "false");
> + let isCodeGenOnly = 1;
>
> // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
> }
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=220393&r1=220392&r2=220393&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Wed Oct 22 11:49:14 2014
> @@ -225,7 +225,7 @@ def AND_ri : ALU32_ri<(outs IntRegs:$dst
> s10ExtPred:$src2))]>, ImmRegRel;
>
> // Nop.
> -let neverHasSideEffects = 1 in
> +let neverHasSideEffects = 1, isCodeGenOnly = 0 in
> def NOP : ALU32_rr<(outs), (ins),
> "nop",
> []>;
> @@ -753,7 +753,7 @@ def HexagonBR_JT: SDNode<"HexagonISD::BR
>
> let InputType = "imm", isBarrier = 1, isPredicable = 1,
> Defs = [PC], isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
> -opExtentBits = 24 in
> +opExtentBits = 24, isCodeGenOnly = 0 in
> class T_JMP <dag InsDag, list<dag> JumpList = []>
> : JInst<(outs), InsDag,
> "jump $dst" , JumpList> {
>
> Modified: llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt?rev=220393&r1=220392&r2=220393&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt (original)
> +++ llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt Wed Oct 22 11:49:14 2014
> @@ -13,13 +13,13 @@
> ;
> ; http://llvm.org/docs/LLVMBuild.html
> ;
> -;===------------------------------------------------------------------------===;
> -
> -[common]
> -subdirectories = InstPrinter MCTargetDesc TargetInfo
> -
> -[component_0]
> -type = TargetGroup
> +;===------------------------------------------------------------------------===;
> +
> +[common]
> +subdirectories = Disassembler InstPrinter MCTargetDesc TargetInfo
> +
> +[component_0]
> +type = TargetGroup
> name = Hexagon
> parent = Target
> has_asmprinter = 1
>
> Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h?rev=220393&r1=220392&r2=220393&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h Wed Oct 22 11:49:14 2014
> @@ -17,12 +17,14 @@
> #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
> #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
>
> -#include "HexagonMCTargetDesc.h"
> -#include "llvm/Support/ErrorHandling.h"
> -
> -namespace llvm {
> -
> -/// HexagonII - This namespace holds all of the target specific flags that
> +#include "HexagonMCTargetDesc.h"
> +#include "llvm/Support/ErrorHandling.h"
> +
> +#include <stdint.h>
> +
> +namespace llvm {
> +
> +/// HexagonII - This namespace holds all of the target specific flags that
> /// instruction info tracks.
> ///
> namespace HexagonII {
> @@ -186,11 +188,20 @@ namespace HexagonII {
> MO_LO16, MO_HI16,
>
> // Offset from the base of the SDA.
> - MO_GPREL
> - };
> -
> -} // End namespace HexagonII.
> -
> -} // End namespace llvm.
> + MO_GPREL
> + };
> +
> + enum class InstParseBits : uint32_t {
> + INST_PARSE_MASK = 0x0000c000,
> + INST_PARSE_PACKET_END = 0x0000c000,
> + INST_PARSE_LOOP_END = 0x00008000,
> + INST_PARSE_NOT_END = 0x00004000,
> + INST_PARSE_DUPLEX = 0x00000000,
> + INST_PARSE_EXTENDER = 0x00000000
> + };
> +
> +} // End namespace HexagonII.
> +
> +} // End namespace llvm.
>
> #endif
>
> Modified: llvm/trunk/lib/Target/Hexagon/Makefile
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Makefile?rev=220393&r1=220392&r2=220393&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/Makefile (original)
> +++ llvm/trunk/lib/Target/Hexagon/Makefile Wed Oct 22 11:49:14 2014
> @@ -14,11 +14,12 @@ TARGET = Hexagon
> BUILT_SOURCES = HexagonGenRegisterInfo.inc \
> HexagonGenInstrInfo.inc \
> HexagonGenAsmWriter.inc \
> - HexagonGenDAGISel.inc HexagonGenSubtargetInfo.inc \
> - HexagonGenCallingConv.inc \
> - HexagonGenDFAPacketizer.inc \
> - HexagonGenMCCodeEmitter.inc
> -
> -DIRS = InstPrinter TargetInfo MCTargetDesc
> -
> -include $(LEVEL)/Makefile.common
> + HexagonGenDAGISel.inc HexagonGenSubtargetInfo.inc \
> + HexagonGenCallingConv.inc \
> + HexagonGenDFAPacketizer.inc \
> + HexagonGenMCCodeEmitter.inc \
> + HexagonGenDisassemblerTables.inc
> +
> +DIRS = InstPrinter TargetInfo MCTargetDesc Disassembler
> +
> +include $(LEVEL)/Makefile.common
>
>
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