[llvm] r220204 - [Thumb2] RFE, SRS and "SUBS pc, lr" are undefined on v7M

[Oliver Stannard]

Author: olista01
Date: Mon Oct 20 10:37:35 2014
New Revision: 220204

URL: http://llvm.org/viewvc/llvm-project?rev=220204&view=rev
Log:
[Thumb2] RFE, SRS and "SUBS pc, lr" are undefined on v7M

These instructions are related to the v7[AR] exception model, and are
not defined on v7M.


Added:
    llvm/trunk/test/MC/ARM/thumb2-exception-return-mclass.s
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=220204&r1=220203&r2=220204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Oct 20 10:37:35 2014
@@ -3757,7 +3757,8 @@ def t2DCPS3 : T2DCPS<0b11, "dcps3">;
 
 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
             string opc, string asm, list<dag> pattern>
-  : T2I<oops, iops, itin, opc, asm, pattern> {
+  : T2I<oops, iops, itin, opc, asm, pattern>,
+    Requires<[IsThumb2,IsNotMClass]> {
   bits<5> mode;
   let Inst{31-25} = 0b1110100;
   let Inst{24-23} = Op;
@@ -3788,7 +3789,8 @@ def : t2InstAlias<"srsia${p} $mode!", (t
 // Return From Exception is a system instruction.
 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
           string opc, string asm, list<dag> pattern>
-  : T2I<oops, iops, itin, opc, asm, pattern> {
+  : T2I<oops, iops, itin, opc, asm, pattern>,
+    Requires<[IsThumb2,IsNotMClass]> {
   let Inst{31-20} = op31_20{11-0};
 
   bits<4> Rn;
@@ -3815,7 +3817,7 @@ let isReturn = 1, isBarrier = 1, isTermi
 def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary,
                         "subs", "\tpc, lr, $imm",
                         [(ARMintretflag imm0_255:$imm)]>,
-                   Requires<[IsThumb2]> {
+                   Requires<[IsThumb2,IsNotMClass]> {
   let Inst{31-8} = 0b111100111101111010001111;
 
   bits<8> imm;

Added: llvm/trunk/test/MC/ARM/thumb2-exception-return-mclass.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2-exception-return-mclass.s?rev=220204&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb2-exception-return-mclass.s (added)
+++ llvm/trunk/test/MC/ARM/thumb2-exception-return-mclass.s Mon Oct 20 10:37:35 2014
@@ -0,0 +1,15 @@
+# RUN: not llvm-mc -triple thumbv7m -assemble < %s 2>&1 | FileCheck %s
+
+  .text
+
+# CHECK: instruction requires: !armv*m
+# CHECK-NEXT: srsdb sp, #7
+  srsdb sp, #7
+
+# CHECK: instruction requires: !armv*m
+# CHECK-NEXT: rfeia r6
+  rfeia r6
+
+# CHECK: instruction requires: !armv*m
+# CHECK-NEXT: subs pc, lr, #42
+  subs pc, lr, #42