[llvm] r220042 - [mips] Add support for COP1's Branch-On-Cond-Likely instructions
Vasileios Kalintiris
Vasileios.Kalintiris at imgtec.com
Fri Oct 17 07:08:29 PDT 2014
Author: vkalintiris
Date: Fri Oct 17 09:08:28 2014
New Revision: 220042
URL: http://llvm.org/viewvc/llvm-project?rev=220042&view=rev
Log:
[mips] Add support for COP1's Branch-On-Cond-Likely instructions
Summary: Depends on D5782
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5802
Added:
llvm/trunk/test/MC/Mips/mips3/invalid-mips4-wrong-error.s
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
llvm/trunk/test/MC/Mips/mips-jump-delay-slots.s
llvm/trunk/test/MC/Mips/mips1/invalid-mips2.s
llvm/trunk/test/MC/Mips/mips1/invalid-mips4-wrong-error.s
llvm/trunk/test/MC/Mips/mips2/invalid-mips4-wrong-error.s
llvm/trunk/test/MC/Mips/mips2/valid.s
llvm/trunk/test/MC/Mips/mips3/valid.s
llvm/trunk/test/MC/Mips/mips32/valid.s
llvm/trunk/test/MC/Mips/mips32r2/valid.s
llvm/trunk/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s
llvm/trunk/test/MC/Mips/mips32r6/invalid-mips2.s
llvm/trunk/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s
llvm/trunk/test/MC/Mips/mips32r6/invalid-mips32.s
llvm/trunk/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s
llvm/trunk/test/MC/Mips/mips32r6/invalid-mips4.s
llvm/trunk/test/MC/Mips/mips4/valid.s
llvm/trunk/test/MC/Mips/mips5/valid.s
llvm/trunk/test/MC/Mips/mips64/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid.s
llvm/trunk/test/MC/Mips/mips64r6/invalid-mips2.s
llvm/trunk/test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s
llvm/trunk/test/MC/Mips/mips64r6/invalid-mips4-wrong-error.s
llvm/trunk/test/MC/Mips/mips64r6/invalid-mips4.s
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Fri Oct 17 09:08:28 2014
@@ -243,14 +243,14 @@ class SWXC1_FT<string opstr, RegisterOpe
}
class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
- SDPatternOperator Op = null_frag> :
+ SDPatternOperator Op = null_frag, bit DelaySlot = 1> :
InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
!strconcat(opstr, "\t$fcc, $offset"),
[(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
FrmFI, opstr> {
let isBranch = 1;
let isTerminator = 1;
- let hasDelaySlot = 1;
+ let hasDelaySlot = DelaySlot;
let Defs = [AT];
}
@@ -562,8 +562,12 @@ def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>,
BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
+def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, IIBranch, MIPS_BRANCH_F, 0>,
+ BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>,
BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
+def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, IIBranch, MIPS_BRANCH_T, 0>,
+ BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
//===----------------------------------------------------------------------===//
// Floating Point Flag Conditions
@@ -629,8 +633,12 @@ def ExtractElementF64_64 : ExtractElemen
//===----------------------------------------------------------------------===//
def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
ISA_MIPS1_NOT_32R6_64R6;
+def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>,
+ ISA_MIPS2_NOT_32R6_64R6;
def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
ISA_MIPS1_NOT_32R6_64R6;
+def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>,
+ ISA_MIPS2_NOT_32R6_64R6;
//===----------------------------------------------------------------------===//
// Floating Point Patterns
Modified: llvm/trunk/test/MC/Mips/mips-jump-delay-slots.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-jump-delay-slots.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips-jump-delay-slots.s (original)
+++ llvm/trunk/test/MC/Mips/mips-jump-delay-slots.s Fri Oct 17 09:08:28 2014
@@ -47,6 +47,24 @@
# CHECK: nop
beqz $11,1332
+ # CHECK: bc1fl 1332
+ # CHECK-NOT: nop
+ bc1fl 1332
+ # CHECK: bc1fl 1332
+ # CHECK-NOT: nop
+ bc1fl $fcc0, 1332
+ # CHECK: bc1fl $fcc3, 1332
+ # CHECK-NOT: nop
+ bc1fl $fcc3, 1332
+ # CHECK: bc1tl 1332
+ # CHECK-NOT: nop
+ bc1tl 1332
+ # CHECK: bc1tl 1332
+ # CHECK-NOT: nop
+ bc1tl $fcc0, 1332
+ # CHECK: bc1tl $fcc3, 1332
+ # CHECK-NOT: nop
+ bc1tl $fcc3, 1332
# CHECK: beql $9, $6, 1332
# CHECK-NOT: nop
beql $9,$6,1332
Modified: llvm/trunk/test/MC/Mips/mips1/invalid-mips2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/invalid-mips2.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/invalid-mips2.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/invalid-mips2.s Fri Oct 17 09:08:28 2014
@@ -5,6 +5,10 @@
# RUN: FileCheck %s < %t1
.set noat
+ bc1fl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bc1fl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bc1tl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bc1tl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
beql $14,$s3,12544 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgezl $4,-6858 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips1/invalid-mips4-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/invalid-mips4-wrong-error.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/invalid-mips4-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/invalid-mips4-wrong-error.s Fri Oct 17 09:08:28 2014
@@ -6,6 +6,8 @@
# RUN: FileCheck %s < %t1
.set noat
+ bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/Mips/mips2/invalid-mips4-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/invalid-mips4-wrong-error.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/invalid-mips4-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/invalid-mips4-wrong-error.s Fri Oct 17 09:08:28 2014
@@ -6,6 +6,8 @@
# RUN: FileCheck %s < %t1
.set noat
+ bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/Mips/mips2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/valid.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/valid.s Fri Oct 17 09:08:28 2014
@@ -18,8 +18,12 @@
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
+ bc1fl $fcc0,50 # CHECK: bc1fl 50 # encoding: [0x45,0x02,0x00,0x0c]
+ bc1fl 50 # CHECK: bc1fl 50 # encoding: [0x45,0x02,0x00,0x0c]
bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
+ bc1tl $fcc0,-8239 # CHECK: bc1tl -8239 # encoding: [0x45,0x03,0xf7,0xf4]
+ bc1tl -8239 # CHECK: bc1tl -8239 # encoding: [0x45,0x03,0xf7,0xf4]
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
Added: llvm/trunk/test/MC/Mips/mips3/invalid-mips4-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips3/invalid-mips4-wrong-error.s?rev=220042&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips3/invalid-mips4-wrong-error.s (added)
+++ llvm/trunk/test/MC/Mips/mips3/invalid-mips4-wrong-error.s Fri Oct 17 09:08:28 2014
@@ -0,0 +1,10 @@
+# Instructions that are invalid and are correctly rejected but use the wrong
+# error message at the moment.
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/Mips/mips3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips3/valid.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips3/valid.s Fri Oct 17 09:08:28 2014
@@ -18,8 +18,12 @@
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
+ bc1fl $fcc0,50 # CHECK: bc1fl 50 # encoding: [0x45,0x02,0x00,0x0c]
+ bc1fl 50 # CHECK: bc1fl 50 # encoding: [0x45,0x02,0x00,0x0c]
bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
+ bc1tl $fcc0,-8239 # CHECK: bc1tl -8239 # encoding: [0x45,0x03,0xf7,0xf4]
+ bc1tl -8239 # CHECK: bc1tl -8239 # encoding: [0x45,0x03,0xf7,0xf4]
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
Modified: llvm/trunk/test/MC/Mips/mips32/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32/valid.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32/valid.s Fri Oct 17 09:08:28 2014
@@ -19,9 +19,15 @@
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
+ bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94]
+ bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94]
+ bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06]
bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
+ bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94]
+ bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94]
+ bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06]
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s Fri Oct 17 09:08:28 2014
@@ -19,9 +19,15 @@
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
+ bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94]
+ bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94]
+ bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06]
bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
+ bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94]
+ bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94]
+ bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06]
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
Modified: llvm/trunk/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s Fri Oct 17 09:08:28 2014
@@ -6,7 +6,5 @@
# RUN: FileCheck %s < %t1
.set noat
- bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
Modified: llvm/trunk/test/MC/Mips/mips32r6/invalid-mips2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/invalid-mips2.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/invalid-mips2.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/invalid-mips2.s Fri Oct 17 09:08:28 2014
@@ -6,6 +6,10 @@
.set noat
addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bc1fl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bc1fl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bc1tl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bc1tl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
beql $14,$s3,12544 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bnel $gp,$s4,5107 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgezl $4,-6858 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s Fri Oct 17 09:08:28 2014
@@ -6,10 +6,6 @@
# RUN: FileCheck %s < %t1
.set noat
- bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- bc1tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- bc1fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
Modified: llvm/trunk/test/MC/Mips/mips32r6/invalid-mips32.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/invalid-mips32.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/invalid-mips32.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/invalid-mips32.s Fri Oct 17 09:08:28 2014
@@ -5,6 +5,8 @@
# RUN: FileCheck %s < %t1
.set noat
+ bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s Fri Oct 17 09:08:28 2014
@@ -6,8 +6,6 @@
# RUN: FileCheck %s < %t1
.set noat
- bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
Modified: llvm/trunk/test/MC/Mips/mips32r6/invalid-mips4.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/invalid-mips4.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/invalid-mips4.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/invalid-mips4.s Fri Oct 17 09:08:28 2014
@@ -5,6 +5,8 @@
# RUN: FileCheck %s < %t1
.set noat
+ bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips4/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips4/valid.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips4/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips4/valid.s Fri Oct 17 09:08:28 2014
@@ -19,9 +19,15 @@
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
+ bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94]
+ bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94]
+ bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06]
bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
+ bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94]
+ bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94]
+ bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06]
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
Modified: llvm/trunk/test/MC/Mips/mips5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/valid.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips5/valid.s Fri Oct 17 09:08:28 2014
@@ -19,9 +19,15 @@
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
+ bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94]
+ bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94]
+ bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06]
bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
+ bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94]
+ bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94]
+ bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06]
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
Modified: llvm/trunk/test/MC/Mips/mips64/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/valid.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/valid.s Fri Oct 17 09:08:28 2014
@@ -19,9 +19,15 @@
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
+ bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94]
+ bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94]
+ bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06]
bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
+ bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94]
+ bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94]
+ bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06]
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Fri Oct 17 09:08:28 2014
@@ -19,9 +19,15 @@
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
+ bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94]
+ bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94]
+ bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06]
bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
+ bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94]
+ bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94]
+ bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06]
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
Modified: llvm/trunk/test/MC/Mips/mips64r6/invalid-mips2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/invalid-mips2.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/invalid-mips2.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/invalid-mips2.s Fri Oct 17 09:08:28 2014
@@ -6,6 +6,10 @@
.set noat
addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bc1fl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bc1fl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bc1tl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bc1tl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
beql $14,$s3,12544 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s Fri Oct 17 09:08:28 2014
@@ -6,10 +6,6 @@
# RUN: FileCheck %s < %t1
.set noat
- bc1fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- bc1tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
Modified: llvm/trunk/test/MC/Mips/mips64r6/invalid-mips4-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/invalid-mips4-wrong-error.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/invalid-mips4-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/invalid-mips4-wrong-error.s Fri Oct 17 09:08:28 2014
@@ -6,8 +6,6 @@
# RUN: FileCheck %s < %t1
.set noat
- bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
Modified: llvm/trunk/test/MC/Mips/mips64r6/invalid-mips4.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/invalid-mips4.s?rev=220042&r1=220041&r2=220042&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/invalid-mips4.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/invalid-mips4.s Fri Oct 17 09:08:28 2014
@@ -5,6 +5,8 @@
# RUN: FileCheck %s < %t1
.set noat
+ bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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