[PATCH] [mips] Add support for COP0's Branch-On-Cond-Likely instructions

[Daniel Sanders]

LGTM with hasDelaySlot=0

================
Comment at: lib/Target/Mips/MipsInstrInfo.td:1197-1198
@@ -1196,2 +1196,4 @@
 def BEQ     : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
+def BEQL    : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd>, BEQ_FM<20>,
+              ISA_MIPS2_NOT_32R6_64R6;
 def BNE     : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
----------------
hasDelaySlot needs to be 0 but CBranch sets it to 1.

http://reviews.llvm.org/D5782