[PATCH] R600: Fix 64-bit integer division

[Tom Stellard]

From: Jan Vesely <jan.vesely at rutgers.edu>

This fixes a failure in one of the oclconform tests.
---
 lib/Target/R600/AMDGPUISelLowering.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
index 63d3ef8..d632aa9 100644
--- a/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -1558,7 +1558,7 @@ void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
     SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
 
     SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
-    SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETGE);
+    SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
 
     DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
 
@@ -1566,7 +1566,7 @@ void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
 
     SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
 
-    REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETGE);
+    REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
     REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
     REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
   }
-- 
1.8.5.5