[PATCH 1/1] R600: Fix integer division

[Tom Stellard]

On Thu, Oct 16, 2014 at 06:37:00PM -0400, Jan Vesely wrote:
> We should use unsigned comparison.
> 

Hi Jan,

Thanks for working on this.  This fixes the failure for me on SI.
I just sent two patches to the list, an updated patch that moves
LowerUDIVREM64 into AMDGPUISelLowering and then your fix applied on top
of it.  Let me know how they look.

Thanks,
Tom


> Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
> ---
>  lib/Target/R600/R600ISelLowering.cpp | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
> index 3b4aed0..4043a9e 100644
> --- a/lib/Target/R600/R600ISelLowering.cpp
> +++ b/lib/Target/R600/R600ISelLowering.cpp
> @@ -924,7 +924,7 @@ void R600TargetLowering::ReplaceNodeResults(SDNode *N,
>        SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
>  
>        SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
> -      SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETGE);
> +      SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
>  
>        DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
>  
> @@ -932,7 +932,7 @@ void R600TargetLowering::ReplaceNodeResults(SDNode *N,
>  
>        SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
>  
> -      REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETGE);
> +      REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
>        REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
>        REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
>      }
> -- 
> 1.9.3
>